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參數(shù)資料
| 型號： | MP1567DQ |
| 廠商： | MONOLITHIC POWER SYSTEMS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.2A Synchronous Rectified Step-Down Converter |
| 中文描述： | 2 A SWITCHING REGULATOR, 800 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | 3 X 3 MM, MO-229VEED-5, QFN-10 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MP1567DQ |
MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
MP1567 Rev. 2.3
1/3/2006
www.MonolithicPower.com
4
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
2006 MPS. All Rights Reserved.
TM
PIN FUNCTIONS
Pin#
Name
Function
Power Switch Boost. BS powers the gate of the high-side N-Channel power MOSFET switch.
Connect a 10nF or greater capacitor between BS and SW.
Internal Power Input. IN supplies the power to the MP1567 through the internal LDO
regulator. Bypass IN to PGND with a 10μF or greater capacitor. Connect IN to the input
source voltage.
Output Switching Node. SW is the source of the high-side N-Channel switch and the drain of
the low-side N-Channel switch. Connect the output LC filter between SW and the output.
Power Ground. PGND is the source of the N-Channel MOSFET synchronous rectifier.
Connect PGND to SGND as close to the MP1567 as possible.
SGND Signal Ground.
Soft-Start Input. Place a capacitor from SS to SGND to set the soft-start period. The MP1567
sources 2μA from SS to the soft-start capacitor at start up. As the voltage at SS rises, the
feedback threshold voltage increases to limit inrush current at start up.
Feedback Input. FB is the inverting input of the internal error amplifier. Connect a resistive
voltage divider from the output voltage to FB to set the output voltage.
Compensation Node. COMP is the output of the error amplifier. Connect a series RC network
to compensate the regulation control loop.
Internal 2.4V Regulator Bypass. Connect a 10nF capacitor between BP and SGND to bypass
the internal regulator. Do not apply any load to BP.
On/Off Control Input. Drive EN high to turn on the MP1567; low to turn it off. For automatic
startup, connect EN to IN.
1
BS
2
IN
3
SW
4
PGND
5
6
SS
7
FB
8
COMP
9
BP
10
EN
OPERATION
The MP1567 measures the output voltage
through an external resistive voltage divider and
compares that to the internal 0.9V reference to
generate the error voltage at COMP. The
current-mode regulator uses the voltage at
COMP and compares it to the inductor current
to regulate the output voltage. The use of
current-mode regulation improves transient
response and improves control loop stability.
At the beginning of each cycle, the high-side
N-Channel MOSFET is turned on, forcing the
inductor current to rise. The current at the drain
of
the
high-side
MOSFET
measured and converted to a voltage by the
current sense amplifier. That voltage is
compared to the error voltage at COMP. When
the inductor current raises sufficiently, the PWM
comparator turns off the high-side switch and
turns on the low-side switch, forcing the
is
internally
inductor current to decrease. The average
inductor current is controlled by the voltage at
COMP, which in turn, is controlled by the output
voltage. Thus the output voltage controls the
inductor current to satisfy the load.
Since the high-side N-Channel MOSFET
requires voltage above V
IN
to drive its gate, a
bootstrap capacitor from SW to BS is required
to drive the high-side MOSFET gate. When SW
is driven low (through the low-side MOSFET),
the BS capacitor is internally charged. The
voltage at BS is applied to the high-side
MOSFET gate to turn it on, and maintains that
voltage until the high-side MOSFET is turned
off and the low-side MOSFET is turned on, and
the cycle repeats. Connect a 10nF or greater
capacitor from BS to SW to drive the high-side
MOSFET gate. Using a larger capacitor does
little to improve performance.
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