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參數(shù)資料
| 型號(hào)： | MN5B02UC |
| 廠商： | PANASONIC CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | OTHER DSP, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大小： | 196K |
| 代理商： | MN5B02UC |
MN5B02UC
10
SDC00048AEM
Electrical Characteristics
(continued)
VDD = 3.0 V to 3.6 V, AVDD = 3.0 V to 3.6 V, VDDI = 1.35 V to 1.65 V, VSS = 0 V, AVSS = 0 V, fTEST = 56 MHz, Ta = –30°C to +85°C
k
90
30
10
VI = VDD
RIL
Pull-down resistor
D21
V
VDD –0.6
IOH = –2.0 mA, VI = VDD or VSS
VOH
Output voltage high level
D19
V
0.4
IOL = 2.0 mA, VI = VDD or VSS
VOL
Output voltage low level
D20
V
VDD
VDD × 0.7
VIH
Input voltage high level
D17
V
VDD × 0.3
0
VIL
Input voltage low level
D18
A
±10
VO = Pull-down,
VI = VDD or VSS , VO = VSS
ILOL
Output leakage current
D22
Input/output LVCMOS level with pull-down resistor: TEST7
Max
Typ
Min
Unit
Limits
Conditions
Symbol
Parameter
Clock Generator (PLL) Characteristic
VDD = 3.3 V, AVDD = 3.3 V, VDDI = 1.50 V, VSS = 0 V, AVSS = 0 V, Ta = 25°C
MHz
19
fIN3
Input frequency
E5
MHz
12.5
fIN2
Input frequency
E3
MHz
100
× 8
FOUT2
Output frequency
E4
MHz
25
fIN1
Input frequency
E1
MHz
100
× 4
FOUT1
Output frequency
E2
MHz
114
× 6
FOUT3
Output frequency
E6
Max
Typ
Min
Unit
Limits
Conditions
Symbol
Parameter
Note) Pin name: TESTIO a0nalog bi-direction pin
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