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參數(shù)資料
| 型號： | MN5B02UC |
| 廠商： | PANASONIC CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | OTHER DSP, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大小： | 196K |
| 代理商： | MN5B02UC |
MN5B02UC
9
SDC00048AEM
Electrical Characteristics
VDD = 3.0 V to 3.6 V, AVDD = 3.0 V to 3.6 V, VDDI = 1.35 V to 1.65 V, VSS = 0 V, AVSS = 0 V, fTEST = 56 MHz, Ta = –30°C to +85°C
V
VDD –0.6
IOH = –2.0 mA, VI = VDD or VSS
VOH
Output voltage high level
D14
V
0.4
IOL = 2.0 mA, VI = VDD or VSS
VOL
Output voltage low level
D15
V
VDD
VDD × 0.7
VIH
Input voltage high level
D12
V
VDD × 0.3
0
VIL
Input voltage low level
D13
k
90
30
10
VI = VDD
RIL
Pull-down resistor
D8
V
VDD × 0.3
0
VIL
Input voltage low level
D4
mA
20
VI (pull up) = Open,
VI (pull down) = Open,
Input pins and bi-directional pins
in the Hi-Z state are
simultaneously connected to
either VDD or VSS input levels.
IDDS
Static supply current
D1
A
±5
VO = Hi-Z, VI = VDD or VSS ,
VO = VDD or VSS
ILO
Output leakage current
D16
A
±10
VI = VSS
ILIL
Input leakage current
D9
V
VDD × 0.3
0
VIL
Input voltage low level
D7
V
VDD
VDD × 0.7
VIH
Input voltage high level
D6
Input LVCMOS level with pull-down resistor: MINTEST, TEST1 to TEST6, SCANMODE, TEST8
A
±5
VI = VDD or VSS
ILI
Input leakage current
D5
V
VDD
VDD × 0.7
VIH
Input voltage high level
D3
Input LVCMOS level: SI, WE, MCK, PLL0, PLL1, SCK, SIF, WCK, MUTE, PSAVE, BYPASS, RESET, BCK
mW
170
85
VI = VDD or VSS , f = 56 MHz,
VDD = 3.3 V, AVDD = 3.3 V,
VDDI = 1.5 V,
External load = 65 pF output
open
PDDO
Operating power
consumption
D2
Input/output LVCMOS level: SDI0 to SDI2, MODE0 to MODE4, SDIF0 to SDIF2
V
0.4
IOL = 4.0 mA, VI = VDD or VSS
VOL
Output voltage low level
D11
V
VDD –0.6
IOH = –4.0 mA, VI = VDD or VSS
VOH
Output voltage high level
D10
Output pushpull: SDO
Max
Typ
Min
Unit
Limits
Conditions
Symbol
Parameter
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