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參數(shù)資料
| 型號： | MMC2001HCAB33B |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 33MHZ 144-LQFP |
| 標準包裝： | 60 |
| 系列： | MCore |
| 核心處理器： | M210 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | ROM |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 809 (CN2011-ZH PDF) |
MOTOROLA
MMC2001 PRODUCT INFORMATION
5
Time-of-Day with Alarm (TOD)
—
Free-running, clocked at LOW_REFCLK/128.
—
Two 32-bit registers count seconds and fractions (1/256) of seconds
—
Unaffected by low power modes
—
Alarm interrupt can be used to exit from any low power state
Periodic Interrupt Timer (PIT)
—
Clocked at LOW_REFCLK/4
—
Count down from modulus latch value (set-and-forget) or free-running
—
Polled or interrupt-driven operation
Watch-Dog Timer (WD)
—
Clocked at LOW_REFCLK/16384
—
Time-out period determined by 6-bit count value
—
Count register re-loaded by each service sequence
INTERRUPT CONTROLLER MODULE
The IC module performs interrupt masking and priority support. Absolute priority of interrupt service
requests is determined by the processor. The IC manages requests from multiple sources and provides an
interface to the processor. It can manage up to 32 interrupt sources, indicates pending interrupt requests,
enables/disables interrupt sources, and determines whether an interrupt is a normal or fast mode interrupt
(fast mode interrupts always have priority). The IC also provides a mechanism for software to schedule
interrupt requests.
DUAL UART MODULE
This module provides two independent and nearly identical (UART0 includes modem RTS and CTS
support, while UART1 does not) serial communications interfaces. Both UARTs support standard serial
communications at normal baud rates and are also compatible with the HPSIR/IrDA Physical
Communication Protocol. Each UART contains independent receivers and transmitters clocked by an
independent clock generator. The generator can be clocked by system clock HI_REFCLK or by an external
clock source on the DTR pin. A 12-bit programmable prescaler is used to generate the baud clock.
The UARTs support full duplex, auto-echo loopback, local loopback, and remote loopback modes. Data
formats are 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits. Four-byte receive buffers and
two-byte transmit buffers minimize CPU service overhead. The module also provides error-detection and
maskable-interrupt capabilities. Each UART can generate an interrupt service request when operational or
error-condition events occur. Interrupts support wake up from low power modes.
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
The ISPI supports a standard, multimaster serial peripheral interface bus, including interrupt-driven
operation, and also supports transfers at programmable intervals to implement timed-event protocols.
The ISPI has three operating modes:
Manual Mode -- typical SPI Master mode operation
Interval Mode -- Manual Mode plus the ability to exchange data at programmed periodic intervals.
Slave Mode -- typical SPI Slave mode operation
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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