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參數(shù)資料
| 型號： | MMC2001HCAB33B |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 33MHZ 144-LQFP |
| 標準包裝： | 60 |
| 系列： | MCore |
| 核心處理器： | M210 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | ROM |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 809 (CN2011-ZH PDF) |
2
MCORE ARCHITECTURAL INFORMATION
MOTOROLA
Figure 1 is a block diagram of the MMC2001 microcontroller. The paragraphs that follow describe the
functional components of the integrated control system.
Figure 1. MMC2001 Block Diagram
MCORE PROCESSOR CORE
The 32-bit MCORE microRISC Engine is the first of a new line of Motorola microprocessor products designed
expressly for embedded control applications. MCORE is a streamlined execution engine that uses many of
the same performance enhancements as mainstream RISC computer designs to minimize system complexity
and overhead. A 16-bit instruction encoding is used to lower memory bandwidth and sustain a high rate of
instruction execution.
The MCORE processor utilizes a four-stage pipeline for instruction execution. The Instruction Fetch,
Instruction Decode/Register File Read, Execute, and Register File Writeback stages operate in an overlapped
fashion, allowing single clock instruction execution for most instructions.
MCORE
RISC CPU
SRAM
20-bit
16-bit
IC
CLK
WDOG
M
E
M
O
RY
CONT
RO
LLER
TOD
RESET
ISPI
OSC
ROM
PIT
OnCE
PWM
DUART
GEN
KE
YP
AD
/GP
IO
INTERRUPT
/ GPIO
Address Bus
Data Bus
256 Kbyte
32 Kbyte
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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