參數(shù)資料
型號: MM908E626AVDWB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝: 17.90 X 7.50 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, SOIC-54
文件頁數(shù): 11/44頁
文件大?。?/td> 833K
代理商: MM908E626AVDWB
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
writing has no effect. Therefore, a high temperature interrupt
cannot be lost due to inadvertent clearing of HTF. Reset
clears the HTF bit. Writing a logic [0] to HTF has no effect.
1 = High temperature condition has occurred.
0 = High temperature condition has not occurred.
LVF—LOW VOLTAGE FLAG BIT
This read/write flag is set on a low voltage condition. Clear
LVF by writing a logic [1] to LVF. If a low voltage condition is
still present while writing a logic [1] to LVF, the writing has no
effect. Therefore, a low voltage interrupt cannot be lost due
to inadvertent clearing of LVF. Reset clears the LVF bit.
Writing a logic [0] to LVF has no effect.
1 = Low voltage condition has occurred.
0 = Low voltage condition has not occurred.
HVF—HIGH VOLTAGE FLAG BIT
This read/write flag is set on a high voltage condition.
Clear HVF by writing a logic [1] to HVF. If high voltage
condition is still present while writing a logic [1] to HVF, the
writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to inadvertent clearing of HVF. Reset
clears the HVF bit. Writing a logic [0] to HVF has no effect.
1 = High voltage condition has occurred.
0 = High voltage condition has not occurred.
OCF—OVER-CURRENT FLAG BIT
This read-only flag is set on an overcurrent condition.
Reset clears the OCF bit. To clear this flag, write a logic [1] to
the appropriate overcurrent flag in the SYSSTAT Register.
See Figure 9, which shows the two signals triggering the
OCF.
1 = High current condition has occurred.
0 = High current condition has not occurred.
OCF
HVDD_OCF
HB_OCF
Figure 9. Principal Implementation for OCF
INTERRUPT MASK REGISTER (IMR)
Bit7
6
5
4
3
2
1
Bit0
Read
Write
Reset
LINIE—LIN LINE INTERRUPT ENABLE BIT
This read/write bit enables CPU interrupts by the LIN flag,
LINF. Reset clears the LINIE bit.
1 = Interrupt requests from LINF flag enabled.
0 = Interrupt requests from LINF flag disabled.
Register Name and Address: IMR - $04
0
LINIE
HTIE
LVIE
HVIE
OCIE
0
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