OPERATIONAL MODES SERIAL SPI INTERFACE The" />
參數(shù)資料
型號(hào)： MM908E625ACDWB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 11/49頁(yè)
文件大?。?/td> 0K
描述： IC QUAD HALF BRDG MCU/LIN 54SOIC
標(biāo)準(zhǔn)包裝： 26
應(yīng)用： 自動(dòng)鏡像控制
核心處理器： HC08
程序存儲(chǔ)器類型： 閃存（16 kB）
控制器系列： 908E
RAM 容量： 512 x 8
接口： SCI，SPI
輸入/輸出數(shù)： 13
電源電壓： 8 V ~ 18 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 54-BSSOP（0.295"，7.50mm 寬）裸露焊盤
包裝： 管件
供應(yīng)商設(shè)備封裝： 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
908E625
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SERIAL SPI INTERFACE
The SPI creates the communication link between the
microcontroller and the 908E625. The interface consists of
four pins. See Figure 9:
SS—Slave Select
MOSI—Master-Out Slave-In
MISO—Master-In Slave-Out
SPSCK—Serial Clock
A complete data transfer via the SPI consists of 2 bytes.
The master sends address and data, slave system status,
and data of the selected address.
Figure 9. SPI Protocol
During the inactive phase of SS, the new data transfer is
prepared. The falling edge on the SS line indicates the start
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
The MISO output changes data on a rising edge of
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of SS.
After a write operation, the transmitted data is latched into
the register by the rising edge of SS. Register read data is
internally latched into the SPI at the time when the parity bit
is transferred. SS HIGH forces MISO to high impedance.
A4:A0
Contains the address of the desired register.
R/W
Contains information about a read or a write operation.
If R/W = 1, the second byte of master contains no valid
information, slave just transmits back register data.
If R/W = 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the SMARTMOS register on rising edge of
SS
.
PARITY P
The parity bit is equal to 0 if the number of 1 bits is an even
number contained within R/W, A4:A0. If the number of 1 bits
is odd, P equals 1. For example, if R/W = 1, A4:A0 = 00001,
then P equals 0.
The parity bit is only evaluated during a write operation.
BIT X
Not used.
MASTER DATA BYTE
Contains data to be written or no valid data during a read
operation.
SLAVE STATUS BYTE
Contains the contents of the System Status Register ($0c)
independent of whether it is a write or read operation or which
register was selected.
SLAVE DATA BYTE
Contains the contents of selected register. During a write
operation it includes the register content prior to a write
operation.
S7
S6
S5
S4
S3
S2
S1
S0
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Read/Write, Address, Parity
Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
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參數(shù)描述
MM908E625ACDWB/R2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
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MM908E626 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication
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