參數(shù)資料
型號: MM908E624ACDWB/R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝: PLASTIC, SOIC-54
文件頁數(shù): 25/34頁
文件大?。?/td> 714K
代理商: MM908E624ACDWB/R
908E624ACDWBTAD
Rev 3.0, 01/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Integrated Triple High-Side
Switch with Embedded MCU
and LIN Serial Communication
for Relay Drivers
Thermal Addendum
Introduction
This thermal addendum is provided as a supplement to the
MM908E624 technical datasheet. The addendum provides thermal
performance information that may be critical in the design and
development of system applications. All electrical, application, and
packaging information is provided in the datasheet.
Packaging and Thermal Considerations
The 908E624ACDWB is offered in a 54-terminal dual die package.
There are two heat sources in the package independently heating
with P1 and P2. This results in two junction temperatures, TJ1 and TJ2,
and a thermal resistance matrix with RθJAmn.
For m, n =1, RθJA11 is the thermal resistance from Junction 1 to
the reference temperature while only heat source 1 is heating with P1.
For m =1, n =2, RθJA12 is the thermal resistance from Junction 1
to the reference temperature while heat source 2 is heating with P2.
This applies to RθJ21 and RθJ22, respectively.
54-TERMINAL
SOICW
908E624ACDWB
DWB SUFFIX
98ASA99294D
54-TERMINAL SOICW
Note
For package dimensions, refer to the
MM908E624 datasheet.
TJ1
TJ2
=
RθJA11
RθJA21
RθJA12
RθJA22
.
P1
P2
The stated values are solely for a thermal performance
comparison of one package to another in a standardized
environment. This methodology is not meant to and will not
predict the performance of a package in an application-
specific environment. Stated values were obtained by
measurement and simulation according to the following
standards:
a. Per JEDEC JESD51-2 at natural convection, still air
condition.
b. 2s2p thermal test board per JEDEC JESD51-7.
c. Per JEDEC JESD51-8, with the board temperature on
the center trace near the center lead.
d. Single layer thermal test board per JEDEC JESD51-3.
e. Thermal resistance between the die junction and the
package top surface; assuming a cold plate mounted on
the package top surface.
Table 1. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip (
°C/W)
m =1,
n =1
m =1, n =2
m =2, n =1
m =2,
n =2
RθJAmn
40
31
36
RθJBmn
25
16
21
RθJAmn
57
47
52
RθJCmn
21
12
16
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