參數(shù)資料
型號(hào)： MM908E621ACDWB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝： 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54
文件頁(yè)數(shù)： 22/62頁(yè)
文件大?。?/td> 917K
代理商： MM908E621ACDWB
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESETS
The 908E621 has four internal and one external reset
source.
Each internal reset event will cause a reset pin low for tRST
(1.25 ms typical), after the reset event is gone.
Figure 15. Internal Reset Routing
RESET SOURCE
High Temperature Reset
The device is protected against high temperature. When
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by bit HTR in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
The HTR can be disabled by bit HTRD in the Interrupt
Mask register.
Note: Disabling the high temperature reset can lead to
destruction of the part in cases of high temperature. This
bit was foreseen for test purposes only!
Watchdog Reset
The WatchDog module generates a reset, because of a
watchdog time-out or wrong watchdog timer reset. Reset is
flagged by bit WDR in the Reset Status Register. A Watchdog
reset event will reset all registers in the SPI excluding the
RSR.
Main VREG Low Voltage Reset
The LVR is related to the Main VDD. In case the voltage
falls below a certain threshold, it will pull down the RST_A
terminal. Reset is flagged by bit LVR in the Reset Status
Register. A LVR event will reset all register in the SPI
excluding the RSR.
Power On Reset
The POR is related to the internal 5V supply. In case the
device detects a power on the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all register
in the SPI including the RSR and set the POR bit.
The Power On Reset circuitry will force the RST_A
terminal low for tRST after the VDD has reached its nominal
value (above LVR Threshold). Also see Figure 10, page 20).
Reset terminal / external Reset
An external reset can be applied by pulling down the
RST_A terminal. The reset event is flagged by bit PINR in the
reset status register.
Reset Status Register
This register contains five flags that shows the source of
the last reset. A power-on reset sets the POR bit and clears
all other bits in the Reset Status Register. All bits can be
cleared by writing a one to the corresponding bit. Uncleared
bits remain set as long as they are not cleared by a power-on
reset or by software.
RSR
WDRE
WD Reset Sensor
VDD
RST_A
SPI REGISTERS
Reset SPI Register
(not RSR)
POR internal VREG
LVR Main VREG
HTRD
HTR Reset Sensor
MONO FLOP
Pulse Duration
after reset event is
removed
Clear RSR and set
POR Bit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MM908E621ACDWB/R2 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror
MM908E621ACDWBR2 功能描述:8位微控制器 -MCU QUAD HB / TRIPLE HS 841B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MM908E621ACPEK 功能描述:8位微控制器 -MCU QUAD H-B/3-HS W/MCU & LI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MM908E621ACPEKR2 功能描述:8位微控制器 -MCU QUAD HB AND TRIPLE HS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MM908E622 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
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