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參數(shù)資料
| 型號： | ML6510CQ-80 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510CQ-80 |
ML6510
REV. 1.0 10/25/2000
15
Applications
Zero skew clock generation
The most advantageous feature of using PACMan is its
ability to deliver multiple copies of the clock to the load
with very low skew. Because of its unique ability in
deskewing, trace length and load consideration are no
longer critical in board design.
Because of the unique deskewing scheme, neither the
trace length nor the device loads need to be equal. This is
true for loads, <20pF. Higher loads can be driven if they
are placed close to the clock chip, to guarantee signal
integrity.
CLOCK
DRIVER
tO–tS2
tO–tS3
tO–tS1
tS1
tS 2
tS3
tS0tS0tS0
ONE
DEVICE
LOAD
TWO
DEVICE
LOAD
THREE
DEVICE
LOAD
Low skew clock distribution
Clock distribution design is usually not a trivial task,
especially when multiple clock chips are needed. By
using closely grouped PACMans, 16 or more clock lines
can be created with low part-to-part skew. Additional
groups of clocks can be clustered and driven from
deskewed clock lines, to minimize the number of long-
distance clock lines.
CLK2
CLK0
CLK1
ML6510
CLK0
CLK1
CLK2
CLK0
CLK1
ML6510
CLK3
TO REMOTE GROUP
OF CLUSTERED LOADS
Board to Board synchronization
Distribution of the synchronous clock could present
significant difficulty at high frequency. With the system
clock generated by the ML6510, a zero skew clock
delivery to a backplane is now possible. By using the
ML6510 slave chip or the ML6510 in slave mode at the
receiver end, a near zero delay clock link can be
accomplished between the mother board and the satellite
boards.
Because the PACMan has frequency doubling capability,
a lower frequency signal can be used to route across a
back plane.
ML6510
(SLAVE MODE)
Example configuration
Shown in Figure 7 is an example configuration using
two ML6510-80 chips in tandem to generate eight 66
MHz clocks and eight 33MHz low-skew clocks from a
66MHz input reference. This requires only the termination
resistors. Configurations are loaded from the internal
ROM. PCB traces 0 to 15 are each 50 impedance and
the load capacitances CL0-CL15 are 0 to 20pF each. No
trace length matching is required among separate clock
outputs. All traces are shown with a series termination at
the output. If ML6510-130’s are used in a master slave
mode the maximum operating frequency will be
120MHz.
LOAD[0-7]
LOAD[8-15]
33 MHz
tSKEWR (or tSKEWB)
tpp2
tSKEWR (or tSKEWB)
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