參數(shù)資料
型號： ML610Q411-XXXWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, UUC95
封裝： 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù)： 142/152頁
文件大?。?/td> 1641K
代理商： ML610Q411-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Contents
Contents – 5
13.1.3
List of Pins ........................................................................................................................................ 13-2
13.2 Description of Registers............................................................................................................................ 13-3
13.2.1
List of Registers ................................................................................................................................ 13-3
13.2.2
Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) .................................................... 13-4
13.2.3
Serial Port Control Register (SIO0CON).......................................................................................... 13-5
13.2.4
Serial Port Mode Register 0 (SIO0MOD0)....................................................................................... 13-6
13.2.5
Serial Port Mode Register 1 (SIO0MOD1)....................................................................................... 13-7
13.3 Description of Operation........................................................................................................................... 13-8
13.3.1
Transmit Operation ........................................................................................................................... 13-8
13.3.2
Receive Operation............................................................................................................................. 13-9
13.3.3
Transmit/Receive Operation ........................................................................................................... 13-10
13.4 Specifying port registers ......................................................................................................................... 13-11
13.4.1
Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ “Master mode” ................ 13-11
13.4.2
Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ ”Slave mode”................... 13-12
13.4.3
Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Master mode” ................ 13-13
13.4.4
Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Slave mode”................... 13-14
Chapter 14
14. UART ........................................................................................................................................................... 14-1
14.1 Overview................................................................................................................................................... 14-1
14.1.1
Features............................................................................................................................................. 14-1
14.1.2
Configuration .................................................................................................................................... 14-1
14.1.3
List of Pins ........................................................................................................................................ 14-1
14.2 Description of Registers............................................................................................................................ 14-2
14.2.1
List of Registers ................................................................................................................................ 14-2
14.2.2
UART0 Transmit/Receive Buffer (UA0BUF)..................................................................................14-3
14.2.3
UART0 Control Register (UA0CON) .............................................................................................. 14-4
14.2.4
UART0 Mode Register 0 (UA0MOD0) ........................................................................................... 14-5
14.2.5
UART0 Mode Register 1 (UA0MOD1) ........................................................................................... 14-6
14.2.6
UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) .......................................................... 14-8
14.2.7
UART0 Status Register (UA0STAT) ............................................................................................... 14-9
14.3 Description of Operation......................................................................................................................... 14-11
14.3.1
Transfer Data Format ...................................................................................................................... 14-11
14.3.2
Baud Rate........................................................................................................................................ 14-12
14.3.3
Transmit Data Direction ................................................................................................................. 14-13
14.3.4
Transmit Operation ......................................................................................................................... 14-14
14.3.5
Receive Operation........................................................................................................................... 14-16
14.4 Specifying port registers ......................................................................................................................... 14-18
14.4.1
Functioning P43(TXD0) and P42(RXD0) as the UART ................................................................ 14-18
14.4.2
Functioning P43(TXD0) and P02(RXD0) as the UART ................................................................ 14-19
Chapter 15
15. I
2C Bus Interface........................................................................................................................................... 15-1
15.1 Overview................................................................................................................................................... 15-1
15.1.1
Features............................................................................................................................................. 15-1
15.1.2
Configuration .................................................................................................................................... 15-1
15.1.3
List of Pins ........................................................................................................................................ 15-1
15.2 Description of Registers............................................................................................................................ 15-2
15.2.1
List of Registers ................................................................................................................................ 15-2
15.2.2
I
2C Bus 0 Receive Register (I2C0RD).............................................................................................. 15-3
15.2.3
I
2C Bus 0 Slave Address Register (I2C0SA) .................................................................................... 15-4
15.2.4
I
2C Bus 0 Transmit Data Register (I2C0TD).................................................................................... 15-5
15.2.5
I
2C Bus 0 Control Register (I2C0CON)............................................................................................ 15-6
15.2.6
I
2C Bus 0 Mode Register (I2C0MOD).............................................................................................. 15-7
15.2.7
I
2C Bus 0 Status Register (I2C0STAT) ............................................................................................ 15-8
15.3 Description of Operation........................................................................................................................... 15-9
15.3.1
Communication Operating Mode...................................................................................................... 15-9
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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