參數(shù)資料
型號： ML610Q411-XXXWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, UUC95
封裝： 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù)： 109/152頁
文件大?。?/td> 1641K
代理商： ML610Q411-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Contents
Contents – 2
4.2.6
Block Control Register 2 (BLKCON2) .............................................................................................. 4-7
4.2.7
Block Control Register 3 (BLKCON3) .............................................................................................. 4-8
4.2.8
Block Control Register 4 (BLKCON4) .............................................................................................. 4-9
4.3
Description of Operation........................................................................................................................... 4-11
4.3.1
Program Run Mode........................................................................................................................... 4-11
4.3.2
HALT Mode ..................................................................................................................................... 4-11
4.3.3
STOP Mode ...................................................................................................................................... 4-12
4.3.3.1
STOP Mode When CPU Operates with Low-Speed Clock........................................................... 4-12
4.3.3.2
STOP Mode When CPU Operates with High-Speed Clock .......................................................... 4-13
4.3.3.3
Note on Return Operation from STOP/HALT Mode .................................................................... 4-14
4.3.4
Block Control Function..................................................................................................................... 4-15
Chapter 5
5.
Interrupts (INTs) ............................................................................................................................................. 5-1
5.1
Overview..................................................................................................................................................... 5-1
5.1.1
Features............................................................................................................................................... 5-1
5.2
Description of Registers.............................................................................................................................. 5-2
5.2.1
List of Registers .................................................................................................................................. 5-2
5.2.2
Interrupt Enable Register 1 (IE1)........................................................................................................ 5-3
5.2.3
Interrupt Enable Register 2 (IE2)........................................................................................................ 5-4
5.2.4
Interrupt Enable Register 3 (IE3)........................................................................................................ 5-5
5.2.5
Interrupt Enable Register 4 (IE4)........................................................................................................ 5-6
5.2.6
Interrupt Enable Register 5 (IE5)........................................................................................................ 5-7
5.2.7
Interrupt Enable Register 6 (IE6)........................................................................................................ 5-8
5.2.8
Interrupt Enable Register 7 (IE7)........................................................................................................ 5-9
5.2.9
Interrupt Request Register 0 (IRQ0) ................................................................................................. 5-10
5.2.10
Interrupt Request Register 1 (IRQ1) ................................................................................................. 5-11
5.2.11
Interrupt Request Register 2 (IRQ2) ................................................................................................. 5-12
5.2.12
Interrupt Request Register 3 (IRQ3) ................................................................................................. 5-13
5.2.13
Interrupt Request Register 4 (IRQ4) ................................................................................................. 5-14
5.2.14
Interrupt Request Register 5 (IRQ5) ................................................................................................. 5-15
5.2.15
Interrupt Request Register 6 (IRQ6) ................................................................................................. 5-16
5.2.16
Interrupt Request Register 7 (IRQ7) ................................................................................................. 5-17
5.3
Description of Operation........................................................................................................................... 5-18
5.3.1
Maskable Interrupt Processing.......................................................................................................... 5-19
5.3.2
Non-Maskable Interrupt Processing.................................................................................................. 5-19
5.3.3
Software Interrupt Processing........................................................................................................... 5-19
5.3.4
Notes on Interrupt Routine................................................................................................................ 5-20
5.3.5
Interrupt Disable State ...................................................................................................................... 5-23
Chapter 6
6.
Clock Generation Circuit ................................................................................................................................ 6-1
6.1
Overview..................................................................................................................................................... 6-1
6.1.1
Features............................................................................................................................................... 6-1
6.1.2
Configuration ...................................................................................................................................... 6-1
6.1.3
List of Pins .......................................................................................................................................... 6-2
6.2
Description of Registers.............................................................................................................................. 6-2
6.2.1
List of Registers .................................................................................................................................. 6-2
6.2.2
Frequency Control Register 0 (FCON0) ............................................................................................. 6-3
6.2.3
Frequency Control Register 1 (FCON1) ............................................................................................. 6-5
6.3
Description of Operation............................................................................................................................. 6-6
6.3.1
Low-Speed Clock ............................................................................................................................... 6-6
6.3.1.1
Low-Speed Clock Generation Circuit ............................................................................................. 6-6
6.3.1.2
Operation of Low-Speed Clock Generation Circuit ........................................................................6-7
6.3.2
High-Speed Clock............................................................................................................................... 6-9
6.3.2.1
500 kHz RC Oscillation................................................................................................................... 6-9
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參數(shù)描述
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