參數(shù)資料
型號: ML2724
英文描述: 2.4GHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
中文描述: 2.4GHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表
文件頁數(shù): 9/26頁
文件大?。?/td> 864K
代理商: ML2724
ML2724
PIN
SIGNAL
NAME
I/O
FUNCTION
DIAGRAM
22
TXOB
O (analog)
Complementary TX RF open-collector
output. This output requires a DC path to
VCCA. For single-ended output
applications, this pin should be
connected to a dummy load that includes
a DC path to VCCA.
TXOB
22
TXO
21
GNDRF
18
DATA
7
AOUT
A (analog)
Multi-function Output. In Analog output
mode this is output drives an off chip
data slicer. In Transmit power control
mode this is an open drain output, which
is pulled low when the TPC bit is serial
register #1, is clear. Transitions on TPC
are synchronized to the falling edge of
RXON. In analog test modes this pin and
the RSSI output become test access
points controlled by the serial control
bus.
31
VSS
VDD
100
7
AOUT
8
TPQ
MUX
VSS
8
TPC
MUX
TPC
AOUT
MUX
30
DIN
I (CMOS)
Transmit Data Input. Drives the transmit
pulse shaping circuits. Serial digital data
on this pin becomes FSK modulation on
the Transmit RF output. The logic timing
on this pin controls data timing. Internal
circuits determine the modulation
deviation. This is a standard CMOS input
referenced to VDD and VSS.
See Pin 1 below.
32
DOUT
O (CMOS)
Serial digital output after demodulation,
chip rate filtering and center data slicing.
A CMOS level output (VSS to VDD) with
controlled slew rates. A low drive output
designed to drive a PCB trace and a
CMOS logic input while generating
minimal RFI. In digital test modes this pin
becomes a test access port controlled by
the serial control bus.
31
VSS
VDD
250
32DOUT
8
DS2724-F-01
FINAL DATASHEET
APRIL 2003
9
相關PDF資料
PDF描述
ML2724DH 2.4GHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
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