參數(shù)資料
型號： MK51DX256ZCMC10R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝： 8 X 8 MM, MAPBGA-121
文件頁數(shù)： 9/72頁
文件大?。?/td> 1005K
代理商： MK51DX256ZCMC10R
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
—
0.7
TBD
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral
clocks disabled.
3. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, but peripherals are not in active operation.
4. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode.
6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash.
7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled
but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.
10. Includes 32kHz oscillator current and RTC operation.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks disabled except FTFL
LVD disabled, USB regulator disabled
No GPIOs toggled
Code execution from flash
General
K51 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
17
相關(guān)PDF資料
PDF描述
MK51DX256ZCMC10 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
MK51N512CLQ100R 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
MK51N512CMD100R 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
MK51N256CLQ100 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
MK51N512CMD100 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MK51DX256ZCYY10 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated measurement engine, Ethernet and LCD
MK51N256CLQ100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK51N256CMD100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK51N512CLL100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
MK51N512CLQ100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*