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參數資料
| 型號： | MK50X256CMC100 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121 |
| 封裝： | 8 X 8 MM, MAPBGA-121 |
| 文件頁數： | 8/69頁 |
| 文件大?。?/td> | 1770K |
| 代理商： | MK50X256CMC100 |
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6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled. Code executing from flash.
7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled.
9. Includes 32kHz oscillator current and RTC operation.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks disabled except FTFL
LVD disabled, USB regulator disabled
No GPIOs toggled
Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
General
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
16
Preliminary
Freescale Semiconductor, Inc.
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