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參數(shù)資料
| 型號(hào)： | MK50X256CMC100 |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121 |
| 封裝： | 8 X 8 MM, MAPBGA-121 |
| 文件頁(yè)數(shù)： | 6/69頁(yè) |
| 文件大?。?/td> | 1770K |
| 代理商： | MK50X256CMC100 |
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5.1.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 100 MHz
Bus and FlexBus clocks = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
RUN → VLLS1 → RUN
RUN → VLLS1
VLLS1 → RUN
—
4.1
123.8
μs
RUN → VLLS2 → RUN
RUN → VLLS2
VLLS2 → RUN
—
4.1
49.3
μs
RUN → VLLS3 → RUN
RUN → VLLS3
VLLS3 → RUN
—
4.1
49.2
μs
RUN → LLS → RUN
RUN → LLS
LLS → RUN
—
4.1
5.9
μs
RUN → STOP → RUN
RUN → STOP
STOP → RUN
—
4.1
4.2
μs
RUN → VLPS → RUN
RUN → VLPS
VLPS → RUN
—
4.1
5.8
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
General
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
14
Preliminary
Freescale Semiconductor, Inc.
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