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參數(shù)資料
| 型號： | MK50DX256ZCMC10 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121 |
| 封裝： | 8 X 8 MM, MAPBGA-121 |
| 文件頁數(shù)： | 70/73頁 |
| 文件大?。?/td> | 1006K |
| 代理商： | MK50DX256ZCMC10 |
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Table 53. Revision History
Rev. No.
Date
Substantial Changes
2
3/2011
Initial public revision
3
3/2011
Added sections that were inadvertently removed in previous revision
4
3/2011
Reworded IIC footnote in "Voltage and Current Operating Requirements" table.
Added paragraph to "Peripheral operating requirements and behaviors" section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
5
6/2011
Changed supported part numbers per new part number scheme
Changed DC injection current specs in "Voltage and current operating requirements"
table
Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage
and current operating behaviors" table
Split Low power stop mode current specs by temperature range in "Power
consumption operating behaviors" table
Changed typical IDD_VBAT spec in "Power consumption operating behaviors" table
Added LPTMR clock specs to "Device clock specifications" table
Changed Minimum external reset pulse width in "General switching specifications"
table
Changed PLL operating current in "MCG specifications" table
Added footnote to PLL period jitter in "MCG specifications" table
Changed Supply current in "Oscillator DC electrical specifications" table
Changed Crystal startup time in "Oscillator frequency specifications" table
Changed Operating voltage in "EzPort switching specifications" table
Changed title of "FlexBus switching specifications" table and added Output valid and
hold specs
Added "FlexBus full range switching specifications" table
Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table
Changed Gain spec in "16-bit ADC with PGA characteristics" table
Added typical Input DC current to "16-bit ADC with PGA characteristics" table
Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA
characteristics" table
Changed Analog comparator initialization delay in "Comparator and 6-bit DAC
electrical specifications"
Changed Code-to-code settling time, DAC output voltage range low, and Temperature
coefficient offset voltage in "12-bit DAC operating behaviors" table
Moved Output resistance to "TRIAMP operating behaviors" tables
Changed Supply current, Input offset current, AC input impedance in "TRIAMP
operating behaviors" tables
Changed Temperature drift and Load regulation in "VREF full-range operating
behaviors" table
Changed Regulator output voltage in "USB VREG electrical specifications" table
Changed ILIM description and specs in "USB VREG electrical specifications" table
Changed DSPI_SCK cycle time specs in "DSPI timing" tables
Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table
Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (high-
speed mode)" table
Changed Reference oscillator current source base current spec and added Low-
power current adder footer in "TSI electrical specifications" table
Revision History
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
72
Preliminary
Freescale Semiconductor, Inc.
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