參數(shù)資料
型號： MK50DX256ZCMC10
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝： 8 X 8 MM, MAPBGA-121
文件頁數(shù)： 27/73頁
文件大小： 1006K
代理商： MK50DX256ZCMC10
Table 20. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
20
TBD
μs
thversscr
Sector Erase high-voltage time
—
20
100
ms
thversblk256k Erase Block high-voltage time for 256 KB
—
160
800
ms
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
Read 1s Block execution time
256 KB data flash
—
1.4
ms
trd1sec2k
Read 1s Section execution time (flash sector)
—
40
μs
tpgmchk
Program Check execution time
—
35
μs
trdrsrc
Read Resource execution time
—
35
μs
tpgm4
Program Longword execution time
—
50
TBD
μs
tersblk256k
Erase Flash Block execution time
256 KB data flash
—
160
800
ms
tersscr
Erase Flash Sector execution time
—
20
100
ms
tpgmsec512
tpgmsec1k
tpgmsec2k
Program Section execution time
512 B flash
1 KB flash
2 KB flash
—
TBD
ms
trd1all
Read 1s All Blocks execution time
—
2.8
ms
trdonce
Read Once execution time
—
35
μs
tpgmonce
Program Once execution time
—
50
TBD
μs
tersall
Erase All Blocks execution time
—
320
1600
ms
tvfykey
Verify Backdoor Access Key execution time
—
35
μs
tswapx01
tswapx02
tswapx04
tswapx08
Swap Control execution time
control code 0x01
control code 0x02
control code 0x04
control code 0x08
—
TBD
μs
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
33
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