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參數(shù)資料
| 型號(hào)： | MK2731-02SLF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 117 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 43K |
| 代理商： | MK2731-02SLF |
MK2731-02A
Low Cost VCXO
MDS2731-02AD
1
Revision 12037
Printed 12/3/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Block Diagram
Description
Features
The MK2731-02 is a low cost, low jitter, high
performance VCXO and PLL clock synthesizer
designed to replace expensive discrete VCXOs.
The on-chip Voltage Controlled Crystal Oscillator
accepts a 0 to 3V input voltage to cause the output
clocks to vary by ±100 ppm. Using MicroClock’s
proprietary VCXO and analog Phase-Locked
Loop (PLL) techniques (patents pending), the
device uses an inexpensive 12.288 MHz or
13.5 MHz pullable crystal input to produce up to
three output clocks.
MicroClock manufactures the largest variety of
Set-Top Box and multimedia clock synthesizers
for all applications. Consult MicroClock to
eliminate VCXOs, crystals and oscillators from
your board.
Packaged in 16 pin narrow SOIC
Uses an inexpensive 12.288 or 13.50 MHz crystal
On-chip VCXO (patent pending) with pull range
of 200ppm (minimum)
VCXO tuning voltage of 0 to 3V
Zero ppm synthesis error in all clocks
25mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
5V operating voltage
Voltage
Controlled
Crystal
Oscillator
PLL/Clock
Synthesis
Circuitry
12.288 MHz or
13.5 MHz
pullable
crystal
X1
X2
VIN
Output
Buffer
Output
Buffer
OE (all outputs)
CLK2
CLK3
S2:0
3
Output
Buffer
CLK1
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