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參數(shù)資料
| 型號(hào)： | MK2751-33STRLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.66 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 42K |
| 代理商： | MK2751-33STRLF |
MK2751-33
MPEG/Set-Top Clock Source
MDS2751-33A
1
Revision 2278
Printed 2/27/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
ICRO
CLOCK
Block Diagram
Description
Features
The MK2751-33 is a low cost, low jitter, high
performance clock synthesizer designed for
MPEG and Set-top box systems. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 27.00MHz crystal or clock input to
produce multiple output clocks including the
processor clock, peripheral clocks, and a selectable
audio clock. The audio clocks are exactly
frequency locked to the 27.00MHz input, and our
patented technique gives zero ppm error, allowing
audio and video to track exactly.
MicroClock manufactures the largest variety of
Set-Top Box and multimedia clock synthesizers
for all applications. Consult MicroClock to
eliminate crystals and oscillators from your board.
Packaged in 16 pin narrow (150 mil) SOIC
Selectable audio sampling frequencies support
32 kHz, 44.1 kHz, and 48 kHz in most DACs
27.00 MHz crystal or clock input
Additional clocks provide selections of 60 MHz,
66.66 MHz, 33 MHz, 30 MHz, and 50 MHz
Patented zero ppm error in audio clocks gives
highest performance audio tracking with video
25mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
3.3V or 5V operating voltage
Pin-pin replacement for MK2751-03 at 3.3 V
(external capacitors
needed for crystal input)
Crystal
Oscillator
VDD
GND
Clock Synthesis
and Control
Circuitry
30.000 MHz or
60.000 MHz
Output
Buffer
27 MHz clock
or crystal
Output
Buffer
50.000 MHz
Output
Buffer
ACLK
Output
Buffer
33.333 MHz or
66.666 MHz
Output
Buffer
27.000 MHz
X2
X1
2
ACS2:0
/
3
BCS
CCS
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