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參數資料
| 型號： | MK2069-04GILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VCXO CLK TRANSLATOR 56-TSSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
8
MK2069-04
REV J 051310
VCXO Gain (KO) vs. XTAL Frequency
Setting the RPV, RV, FV and SV Divider Values
in the VCXO PLL
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response software
available from IDT, increasing FV or SV decreases both
bandwidth and damping factor. Many applications require
that SV = 1. In these cases, one way to decrease loop
bandwidth is to increase the value of FV, which is
accompanied by an increase in the value of RPV and/or RV
to maintain the same PLL frequency multiplication ratio.
However, the phase detector frequency, FPD, also needs to
be considered. FPD is equal to the input frequency divided
by the value of the RPV x RV. FPD should be typically at least
20x the loop bandwidth to prevent loop modulation (phase
noise) by the phase detector frequency. The phase detector
jitter tolerance limit (use 0.4UI) and input phase noise
frequency aliasing should be considerations as well.
Example Loop Filter Component Value
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy wander
transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer
such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK
10
20
15
25
3 0
2000
3000
4000
5000
6000
1000
C rys ta l Freq uency, M H z
VC
XO
G
a
in
(
K
O
),
H
z
p
e
r
V
o
lt
Phase
Detector
Frequency
Xtal
Freq
(MHz)
SV
Div
VCLK
(MHz)
FV
Div
RSET
RS
CS
CP
Loop
BW
(-3dB)
Loop
Damp.
Passband
Peaking
Note
8 kHz
19.44
1
19.44
2430 1 M
Ω 560 kΩ 1 μF 4.7 nF 22 Hz
4.0
0.15dB at 1Hz
1
8 kHz
19.44
1
19.44
2430 1 M
Ω 560 kΩ 0.1 μF 4.7 nF 27 Hz
1.4
1.2dB at 6Hz
2
8 kHz
22.368
1
22.368 2796 1 M
Ω 680 kΩ 1 μF 4.7 nF 20 Hz
4.5
0.12dB at 1Hz
3
19.44 MHz
19.44
1
19.44
128
1 M
Ω 27 kΩ
1
μF
47 nF
25 Hz
0.85
1.8dB at 8Hz
4
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| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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