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參數(shù)資料
| 型號： | MK2069-04GILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 0K |
| 描述： | IC VCXO CLK TRANSLATOR 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
18
MK2069-04
REV J 051310
Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may
result in increased output phase noise.
Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the
attempt of the PLL to lock to 0 Hz.
Note 3: The minimum practical phase detector frequency is 1 kHz. Through proper loop filter design lower input
frequencies may be possible. Input frequencies as low as 400 Hz have been tested.
Note 4: A higher input clock frequency can be used when RPV divider = 8.
Note 5: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period.
Note 6: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the
external VCXO PLL loop filter.
Output Rise Time, VCLK and
RCLK
tOR
0.8 to 2.0 V, CL=15 pF
1.5
2
ns
Output Fall Time, VCLK and
RCLK
tOF
2.0 to 0.8 V, CL=15 pF
1.5
2
ns
Output Rise Time, TCLK
tOR
0.8 to 2.0 V, CL=15 pF
0.75
1
ns
Output Fall Time, TCLK
tOF
2.0 to 0.8 V, CL=15 pF
0.75
1
ns
Skew, ICLK to VCLK (Note 6)
tIV
Rising edges, CL=15 pF
-5
2.5
+10
ns
Skew, ICLK to RCLK (Note 6)
tIV
Rising edges, CL=15 pF
+5
10
+20
ns
Skew, ICLK to TCLK (Note 6)
tVT
Rising edges, CL=15 pF
-5
1.5
+10
ns
Nominal Output Impedance
ZOUT
20
Ω
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
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| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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