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參數(shù)資料
| 型號(hào)： | MK2049-01SI |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | MK2049-01SI |
MK2049-01
Communications Clock PLL
MDS 2049-01 K
4
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
OPERATING MODES
The MK2049-01 has two operating modes: External and Loop Timing. Although both modes use an input clock to
generate various output clocks, there are important differences in their input requirements.
External Mode
The MK2049-01 accepts an external 8 kHz clock and will produce a number of common communication clock
frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10
ns is acceptable.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1 and E1
inputs, the CLK1 output will be the same as the input frequency, with CLK2 at twice the input frequency. For T3 and
E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the input frequency.
FREQUENCY LOCKING TO THE INPUT
In both modes, the output clocks are frequency-locked to the input. The output will remain at the specified output
frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For
example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by
up to 60 ppm and still have the output clock remain frequency-locked.
INPUT AND OUTPUT SYNCHRONIZATION
The rising edges of CLK1 and CLK2 do not have a fixed phase alignment with the rising edge of ICLK. Each time
the device is powered-up, the phase relationship could change. Refer to one of the other MK2049 versions (e.g.,
MK2049-02, -03, -34) if input-output phase alignment is important in your application.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-01SILF | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-01SILF | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-36SILF | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SILFTR | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SILF | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-01SITR | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Communications Clock PLL |
| MK2049-01STR | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 20SOIC - Tape and Reel |
| MK2049-02 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Communications Clock PLLs |
| MK2049-02S | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Communications Clock PLLs |
| MK2049-02SI | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Communications Clock PLLs |
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