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參數(shù)資料
| 型號： | MK2049-44SILFTR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 176K |
| 代理商： | MK2049-44SILFTR |
MK2049-44
MDS 2049-44 A
1
Revision 050203
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
3.3V Communications Clock PLL
Description
The MK2049-44 is a dual Phase-Locked Loop (PLL)
device which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate
input jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop
filter component selection.
Buffer Mode accepts a 10 to 50MHz input and will
provide a jitter attenuated output at 0.5 x ICLK, 1 x
ICLK or 2 x ICLK. In this mode the MK2049-44 is ideal
for filtering jitter from high frequency clocks.
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This
allows for the generation of clocks frequency-locked to
an 8 kHz backplane clock, simplifying clock
synchronization in communications systems.
ICS can customize these devices for many other
different frequencies. Contact your ICS representative
for more details.
Features
Packaged in 20 pin SOIC
3.3 V + 5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4,
and 4E
Accepts multiple inputs: 8 kHz backplane clock, or 10
to 50 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 - 50 MHz
input and x1 / x0.5 or x1 / x2 outputs
Exact internal ratios enable zero ppm error
Block Diagram
Charge
Pump
VCXO
X2
X1
ISET
CAP2
Feedback
Divider (N)
Reference
Divider
(used in buffer
mode only)
ICLK
Reference
Divider
Phase
Detector
VCXO
PLL
Feedback
Divider
VCO
Translator
PLL
CLK
CAP1
Output
Divider
Divide
by 2
CLK/2
8k
R
S
R
SET
C
P
C
S
Optional Crystal Load Caps
Divider Value
Look-up Table
FS3:0
4
C
L
C
L
External Pullable Crystal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-44SILF | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SITR | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SILF | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-45 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3V Communications Clock PLL |
| MK2049-45ASI | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-45ASILF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2049-45ASILFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2049-45ASITR | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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