參數(shù)資料
型號: MK1574-01SLFTR
元件分類: 時鐘及定時
英文描述: PLL BASED CLOCK DRIVER, PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 5/8頁
文件大小: 188K
代理商: MK1574-01SLFTR
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
MDS 1574-01 E
5
Revision 062105
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
MK1574-01
AC Electrical Characteristics
VDD = 5 V,
Ambient Temperature 0 to +70
°C, unless stated otherwise
Note 1: All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.
Thermal Characteristics
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the
dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a
high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine
the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore
a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and
X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the
system to increase the output jitter because the mechanical energy is converted directly to voltage noise
on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter
components are calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7).
The loop bandwidth is set by the capacitor C and the constant K1 using the formula:
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency
fIN
8.000
kHz
Output Clock Rise Time
tOR
0.8 to 2.0 V
1.5
ns
Output Clock Fall Time
tOF
2.0 to 0.8 V
1.5
ns
Output Clock Duty Cycle,
High time
tDC
At VDD/2
40
49 to 51
60
%
Absolute Clock Period
Jitter
1ns
Actual Mean Frequency
Error Versus Target (note
1)
Any clock selection
0
ppm
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θ
JA
Still air
120
°C/W
θ
JA
1 m/s air flow
115
°C/W
θ
JA
3 m/s air flow
105
°C/W
Thermal Resistance Junction to Case
θ
JC
58
°C/W
BW (Hz) =
C
K1
Equation 1
相關(guān)PDF資料
PDF描述
MK1574-01S PLL BASED CLOCK DRIVER, PDSO16
MK1574-01SILF PLL BASED CLOCK DRIVER, PDSO16
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MK1574-01SLFTR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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