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參數(shù)資料
| 型號： | MK1574-01SLFTR |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 188K |
| 代理商： | MK1574-01SLFTR |
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
MDS 1574-01 E
3
Revision 062105
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
MK1574-01
Pin Descriptions
External Components
The MK1574-01 requires a minimum number of external components for proper operation. An RC network
(see the section “Loop Bandwidth and Loop Filter Component Selection”) should be connected between
CAP1 and CAP2 as close tot he device as possible. Decoupling capacitors of 0.01F should be connected
between VDD and GND on pins 2, 3, 5 and 7, as close to the device as possible. A series termination
resistor of 33
may be used close to each clock output pin to reduce reflections.
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
Input
Clock input. Connect to an 8 kHz clock input.
2
VDD
Power Connect to 3.3 V.
3
VDD
Power Connect to 3.3 V.
4
CAP1
Input
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP2. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
5
GND
Power Connect to ground.
6
CAP2
Power Connect to a ceramic capacitor and a resistor in series between this pin and
CAP1. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
7
GND
Power Connect to ground.
8
FS0
Input
Frequency select 0. Determines CLK outputs per table above.
9
8KOUT
Output Recovered 8 kHz output clock. Can be low jitter, better duty cycle than clock
input.
10
CLK1
Output Clock 1 determined by status of FS3:0 per table above.
11
CLK2
Output Clock 2 determined by status of FS3:0 per table above.
12
CLK3
Output Clock 3 determined by status of FS3:0 per table above.
13
FS1
Input
Frequency select 1. Determines CLK outputs per table above.
14
FS2
Input
Frequency select 2. Determines CLK outputs per table above.
15
NC
—
No connect. Do not connect anything to this pin.
16
FS3
Input
Frequency select 3. Determines CLK outputs per table above.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK1574-01S | PLL BASED CLOCK DRIVER, PDSO16 |
| MK1574-01SILF | PLL BASED CLOCK DRIVER, PDSO16 |
| MK1574-01SILFTR | PLL BASED CLOCK DRIVER, PDSO16 |
| MK1574-01SLFTR | 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MK1575-01GLFTR | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1574-01STR | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK1575-01G | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GI | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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