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參數(shù)資料
| 型號(hào)： | MIC3001GML TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 65/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FOM MANAGEMENT W/CALIBR 24MLF |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | SDHj Sonet |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤(pán)，24-MLF? |
| 供應(yīng)商設(shè)備封裝： | 24-MLF?（4x4） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC3001GMLTR MIC3001GMLTR-ND |
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CS4205
68
DS489PP4
13. GROUNDING AND LAYOUT
Figure 33 on page 69 shows the conceptual layout
for the CS4205 in XTAL or OSC clocking modes.
The decoupling capacitors should be located phys-
ically as close to the pins as possible. Also, note the
connection of the REFFLT decoupling capacitors
to the ground return trace connected directly to the
ground return pin, AVss1.
It is strongly recommended that separate analog
and digital ground planes be used. Separate ground
planes keep digital noise and return currents from
modulating the CS4205 ground potential and de-
grading performance. The digital ground pins
should be connected to the digital ground plane and
kept separate from the analog ground connections
of the CS4205 and any other external analog cir-
cuitry. All analog components and traces should be
located over the analog ground plane and all digital
components and traces should be located over the
digital ground plane.
The common connection point between the two
ground planes (required to maintain a common
ground voltage potential) should be located under
the CS4205. The AC-link digital interface connec-
tion traces should be routed such that the digital
ground plane lies underneath these signals (on the
internal ground layer). This applies along the entire
length of these traces from the AC ’97 controller to
the CS4205.
Refer to the Application Note AN18: Layout and
Design Rules for Data Converters and Other
Mixed Signal Devices [2] for more information on
layout and design rules.
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