MIC3000 Micrel Electrical Characteristics Symbol Parameter Condition Min Typ Max Units Serial Data I/O Pin," />
參數(shù)資料
型號(hào)： MIC3000BML TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 3/58頁(yè)
文件大?。?/td> 0K
描述： IC TXRX OPTICAL MANAGEMENT 24MLF
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤，24-MLF?
供應(yīng)商設(shè)備封裝： 24-MLF?（4x4）
包裝： 帶卷 (TR)
其它名稱： MIC3000BMLTR
MIC3000BMLTR-ND
October 2004
11
M9999-101204
MIC3000
Micrel
Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Serial Data I/O Pin, DATA
VOL
Low Output Voltage
IOL = 3mA
0.4
V
IOL = 6mA
0.6
V
VIL
Low Input Voltage
0.8
V
VIH
High Input Voltage
2.1
V
ILEAK
Input Current
±1
A
CIN
Input Capacitance
Note 4
10
pF
Serial Clock Input, CLK
VIL
Low Input Voltage
2.7V - VDD - 3.6V
0.8
V
VIH
High Input Voltage
2.7V - VDD - 3.6V
2.1
V
ILEAK
Input Current
±1
A
CIN
Input Capacitance
Note 4
10
pF
Serial Interface Timing(4)
t1
CLK (clock) Period
2.5
s
t2
Data in Setup Time to CLK High
100
ns
t3
Data Out Stable After CLK Low
300
ns
t4
DATA Low Setup Time to CLK Low
Start Condition
100
ns
t5
DATA High Hold Time After CLK High Stop Condition
100
ns
tDATA
Data Ready Time
From power on to completion of one set of
400
ms
ADC conversions; analog data available via
serial interface.
tTO
BUS Timeout
CLK Low
25
30
35
ms
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Guaranteed by design and/or testing of related parameters. Not 100% tested in production.
5. The MIC3000 will attempt to enter its shutdown state when VDD falls below VUVLO. This operation requires time to complete. If the supply voltage falls
too rapidly, the operation may not be completed.
6. Does not include quantization error.
7. Final test on outgoing product is performed at TA = +25°C.
8. The MIC3000 will not respond to serial bus transactions during an EEPROM write-cycle. The host will receive a NACK during tWR.
Timing Diagram
t1
t4
t2
t5
t3
DATA
(Output)
DATA
(Input)
CLK
Serial Interface Timing
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