參數(shù)資料
型號(hào): MH28D72KLG-10
廠商: Mitsubishi Electric Corporation
英文描述: 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述: 9663676416位(134217728 - Word的72位),雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù): 24/39頁
文件大小: 337K
代理商: MH28D72KLG-10
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
24
READ with Auto-Precharge (BL=8, CL=2(Discrete))
Module input and output timing.
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
1
00
ACT
Xb
Xb
00
Internal precharge start
(BL/2+1 in case of Module)
tRCD
tRP
BL/2 + tRP
BL/2
DQS
/CLK
CLK
Qa0 Qa1 Qa2 Qa3
Qa4 Qa5 Qa6 Qa7
READ Auto-Precharge Timing (BL=8)
Command
ACT
READ
DQ
CL=2.5
BL/2
DQ
CL=2
Qa0
/CLK
CLK
Qa0 Qa1 Qa2
Qa3 Qa4 Qa5 Qa6 Qa7
Qa1 Qa2 Qa3 Qa4
Qa5 Qa6 Qa7
Module input and output timing.
Discrete
Internal Precharge Start Timing
(In case of module, Precharge start at BL/2+1)
CL=3.5
CL=3
Module
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