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MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
17
Figure Number
Title
Page
Figure 3-125. BUFCSnR of a Single Transmit Message Buffer for the Static Segment . . . . . . . . . . . 151
Figure 3-126. BUFCSnR of a CC Part Transmit Message Buffer of a Double Tx Buffer
for Dynamic and Static Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 3-127. BUFCSnR of FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 3-128. CCFnR, Transmit and Receive Message Buffer Filter Registers. . . . . . . . . . . . . . . . . . 158
Figure 3-129. CCFnR, CC Part Buffer of a Double Transmit Message Buffer Filter Registers. . . . . . 158
Figure 3-130. CCFnR, FIFO Buffer Filter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 3-131. Buffer Control, Configuration, Status/Filtering Register Set for Transmit/Receive
Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 3-132. Buffer Control, Configuration, Status/Filtering Register Set for Receive FIFO Buffers163
Figure 3-133. Buffer Busy Bit Timing for a Transmit Message Buffer . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 3-134. Example of a Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 3-135. Transition Scheme Between Different Buffer Types Depending on Operational
Mode of CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 3-136. Operations During a Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 3-137. Operations with a Single Transmit Message Buffer during an Event Type of
Transmission for a Static Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 3-138. Double Transmit Message Buffer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 3-139. Doubled Buffer Data Collection with State Driven Transmit Operation . . . . . . . . . . . . 184
Figure 3-140. Doubled Buffer Data collection with Event Driven Transmit Operation. . . . . . . . . . . . 185
Figure 3-141. FIFO Status (Empty, Not Empty, Overrun) — Example of FIFO with Three
Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 3-142. Connecting MFR4200 to MPC5xx Using the AMI (Example) . . . . . . . . . . . . . . . . . . . 190
Figure 3-143. Connecting MFR4200 to MAC71xx Using the AMI (Example). . . . . . . . . . . . . . . . . . 191
Figure 3-144. Connecting MFR4200 to DSP56F83x (Hawk) Using the AMI (Example) . . . . . . . . . . 191
Figure 3-145. FlexRay CC to HCS12 Device Connection with HCS12 EBI Paged Mode Support. . . 193
Figure 3-146. FlexRay CC to HCS12 Device Connection with HCS12 EBI Unpaged Mode Support 194
Figure 3-147. HCS12 interface Address Decoding and Internal CS Signal Generation. . . . . . . . . . . . 195
Figure 3-148. Timing Diagram of CC State Transition from Configuration State to Normal State. . . 200
Figure 3-149. Start of Communication Cycle and Start of Offset Correction Functions Timing. . . . . 204
Figure 3-150. Timing for Debug Functions with Three EXTAL or CC_CLK Clock Cycles
of High State (Logic “1“) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 3-151. Slot Start in Static Segment Function Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 4-1.
VREG3V3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 5-1.
Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 5-2.
Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 5-3.
External Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216