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參數(shù)資料
| 型號： | MF601G2-02BJxx |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 2.5 Flash Drive |
| 中文描述： | 2.5閃存盤 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 145K |
| 代理商： | MF601G2-02BJXX |
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Oct.2000
. Rev. 0.3
MITSUBISHI
ELECTRIC
8/18
Drive/Head Register
The Drive/Head register is used to specify the selected drive
of a pair of drives sharing a set of registers.
DD7
X
DD6
LBA
DD5
X
DD4
DRV
DD3
HS3
LBA27
DD2
HS2
LBA26
DD1
HS1
LBA25
DD0
HS0
LBA2
4
Field
X
LBA
function
Undefined . “0” or “1”.
This bit is “0” for CHS addressing and “1” for Logical
Block addressing.
This bit is number of the drive which the host has
selected. When DRV is cleared, Drive0 is selected. When
DRV is set, Drive1 is selected. The card is selected to be
Drive0 or to be Drive1 using the “Copy” field of the PC
Card Socket Copy Register.
HS3-0 of the head number in CHS addressing or
LBA27-24 of the Logical Block Number in LBA
addressing.
DRV
HS3-0
LBA27-24
Status and Alternate Status Registers
The Status register and the Alternate Status register return
the card status when read by the host. Reading the Status
register clears a pending interrupt request while reading the
Alternate Status register does not. The Status register and the
Alternate Status register are read only registers.
DD7
BSY
DD6
DRDY
DD5
DWF
DD4
DSC
DD3
DRQ
DD2
CORR
DD1
IDX
DD0
ERR
Field
BSY
function
This bit is set when the card internal operation is
executing. When this bit is set to “1”, other bits in this
register are invalid.
DRDY indicates whether the card is capable of
performing card operations.
This bit, if set, indicates a write fault has occurred.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred
between the host and Data register.
This bit is set when a correctable data error has been
occurred and the data has been corrected.
This bit is always set to “0”.
This bit is set when the previous command has ended in
some type of error. The error information is set in the
other Status register bits or Error register. This bit is
cleared by the next command.
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
Command Register
The Command register contains the command code being
sent to the device. Command execution begins immediately
after this register is written. The Command register is a write
only register.
DD7
DD6
DD5
DD4
Command
DD3
DD2
DD1
DD0
Device Control Register
This register is used to control the card interrupt request and
to issue a soft reset to the card. The Device Control register
is a write only register.
DD7
X
DD6
X
DD5
X
DD4
X
DD3
1
DD2
SRST
DD1
nIEN
DD0
0
Field
X
1
SRST
function
don’t care.
This bit is set to “1”.
This bit is set to “1” in order to force the card to perform a
Command Block Reset operation. This does not change the
Card Configuration registers as a Hardware Reset does.
The card remains in Reset until this bit is reset to “0”.
This bit is used for enabling IREQ#. When this bit is set to
“0”, IREQ# is enabled. When this bit is set to “1”, IREQ# is
disabled.
This bit is set to “0”.
nIEN
0
Drive Address Register
This register is provided for compatibility with the AT disk
drive interface.
DD7
X
DD6
nWTG
DD5
DD4
DD3
DD2
DD1
nDS1
DD0
nDS0
nHS3-0
Field
X
nWTG
function
This bit is unknown.
This bit is set to “0” when a Flash write operation is in
progress, otherwise it is set to “1”.
These bits is the negative value of Head Select bits in
Drive/Head register.
This bit is set to “0” when Slave drive is active and selected.
This bit is set to “0” when Master drive is active and selected.
nHS3-0
nDS1
nDS0
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