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參數(shù)資料
| 型號(hào)： | MF601G2-02BJxx |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 2.5 Flash Drive |
| 中文描述： | 2.5閃存盤 |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大小： | 145K |
| 代理商： | MF601G2-02BJXX |
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MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Oct.2000
. Rev. 0.3
MITSUBISHI
ELECTRIC
7/18
ATA Register Specifications
Data Register
This register is a 16 bit register which is used to transfer data
blocks between the card data buffer and the host. Data may
be transferred by either a series of word accesses to the Data
register or a series of byte accesses to the Data register.
DD15
DD1
4
DD1
3
DD1
2
Data Word
Odd Data Byte
DD1
1
DD1
0
DD9
DD8
DD7
DD6
DD5
DD4
Data Word
Data Byte
DD3
DD2
DD1
DD0
Error Register
This register contains additional information about the
source of an error which has occurred in processing of the
preceding command. This register should be checked by the
host when ERR bit in the Status register is set. The Error
register is a read only register.
DD7
BBK
DD6
UNC
DD5
0
DD4
IDNF
DD3
0
DD2
ABRT
DD1
0
DD0
AMNF
Field
BBK
function
This bit is set when a Bad Block is detected in requested ID
field. Host can not read/write on data area that is marked as
a Bad Block.
This bit is set when Uncorrectable error is occurred at
reading the card.
The requested sector ID is in error or cannot be found.
This bit is set if the command has been aborted because of
the card status condition. (Not ready, Write fault, etc.) or
when an invalid command has been issued.
This bit is set in case of a general error.
UNC
IDNF
ABRT
AMNF
Feature Register
This register is written by the host to provide command
specific information to the drive regarding features of the
drive which the host wish to utilize. The Feature register is a
write only register.
DD7
DD6
DD5
DD4
Feature byte
DD3
DD2
DD1
DD0
Sector Count Register
This register is written by the host with the number of
sectors or blocks to be processed in the subsequent
command. After the command is complete, the host may
read this register to obtain the count of sectors left
unprocessed by the command.
DD7
DD6
DD5
DD4
Sector Count
DD3
DD2
DD1
DD0
Sector Number Register
This register is written by the host with the starting sector
number to be used in the subsequent Cylinder-Head-Sector
command. After the command is complete, the host may
read the final sector number from this register. When logical
block addressing is used, this register is written by the host
with bit7 to 0 of the starting logical block number and
contains bit7 to 0 of the final logical block number after the
command is complete.
DD7
DD6
DD5
DD4
Sector Number
DD3
DD2
DD1
DD0
Logical Block Number bits A07-A00(LBA Addressing)
Cylinder Low Register
This register is written by the host with the low-order byte of
the starting cylinder address to be used in the subsequent
Cylinder-Head-Sector command. After the command is
complete, the host may read the low-order byte of the final
cylinder number from this register. When logical block
addressing is used, this register is written by the host with
bits15 to 8 of the starting logical block number and contains
bits15 to 8 of the final logical block number after the
command complete.
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Cylinder Low Byte
Logical Block Number bits A15-A08(LBA Addressing)
Cylinder High Register
This register is written by the host with the high-order byte
of the starting cylinder address to be used in the subsequent
Cylinder-Head-Sector command. After the command is
complete, the host may read the high-order byte of the final
cylinder number from this register. When logical block
addressing is used, this register is written by the host with
bits 23 to 16 of the starting logical block number and
contains bits23 to 16 of the final logical block number after
the command is complete.
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Cylinder High Byte
Logical Block Number bits A23-A16(LBA Addressing)
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