參數(shù)資料
型號： MF280C51-30D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 98/176頁
文件大?。?/td> 2962K
代理商： MF280C51-30D
28
2535J–AVR–08/10
ATtiny13
6.4.2
CLKPR – Clock Prescale Register
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
Bits 6:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.hee setting. The Application software must ensure that a sufficient division factor
is chosen if the selected clock source has a higher frequency than the maximum frequency of
the device at the present operating conditions. The device is shipped with the CKDIV8 fuse
programmed.
Bit
7
6
5
4
3
2
1
0
CLKPCE
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
Table 6-8.
Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
00
0
1
00
0
1
2
00
1
0
4
00
1
8
01
0
16
01
0
1
32
01
1
0
64
01
1
128
10
0
256
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