參數(shù)資料
型號(hào): MF10CCN
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): 運(yùn)動(dòng)控制電子
英文描述: Universal Monolithic Dual Switched Capacitor Filter
中文描述: SWITCHED CAPACITOR FILTER, BUTTERWORTH/BESSEL/CHEBYSHEV, UNIVERSAL, PDIP20
封裝: PLASTIC, DIP-20
文件頁(yè)數(shù): 5/20頁(yè)
文件大?。?/td> 364K
代理商: MF10CCN
Typical Performance Characteristics
(Continued)
vs Clock Frequency
f
CLK
/f
O
Deviation
vs Clock Frequency
f
CLK
/f
O
Deviation
Deviation off
CLK
vs Nominal Q
f
O
Deviation off
CLK
vs Nominal Q
f
O
TL/H/10399–3
Pin Descriptions
LP(1,20), BP(2,19), The second order lowpass, bandpass
N/AP/HP(3,18)
and
notch/allpass/highpass
These outputs can typically sink 1.5 mA
and source 3 mA. Each output typically
swings to within 1V of each supply.
outputs.
INV(4,17)
The inverting input of the summing op-
amp of each filter. These are high im-
pedance inputs, but the non-inverting in-
put is internally tied to AGND, making
INV
A
and INV
B
behave like summing
junctions (low impedance, current in-
puts).
S1(5,16)
S1 is a signal input pin used in the all-
pass filter configurations (see modes 4
and 5). The pin should be driven with a
source impedance of less than 1 k
X
. If
S1 is not driven with a signal it should be
tied to AGND (mid-supply).
S
A/B
(6)
This pin activates a switch that connects
one of the inputs of each filter’s second
summer to either AGND (S
A/B
tied to
V
b
) or to the lowpass (LP) output (S
A/B
tied to V
a
). This offers the flexibility
needed for configuring the filter in its
various modes of operation.
V
A
a
(7),V
D
a
(8)
Analog positive supply and digital posi-
tive supply. These pins are internally
connected through the IC substrate and
therefore V
A
a
and V
D
a
should be de-
rived from the same power supply
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and by-
passed by a single capacitor.
V
A
b
(14), V
D
b
(13) Analog and digital negative supplies.
The same comments as for V
A
V
D
and
apply here.
5
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