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MDS213
Data Sheet
86
Zarlink Semiconductor Inc.
Bit [11:0]
QSW[2:0]
Transmission Queue Service Weight for queue 2, 1 & 0. (4 bit each)
Defines the service rate for each queue QR0-QR3
QR0 : QR1 : QR2 : QR3
QR0 = QSW0*(QSW1+1)* (QSW2+1)
QR1 = QSW1*(QSW2+1)
QR2 = QSW2
QR3 = 1
Note:
Queue 0 has the highest priority. Queue Size is defined in the Queue Control Table
18.2.8.3 ATTL - Transmission Timing Control
Access:
Non-Zero-Wait-State,
Direct Access,
Write/Read
Address:
h650
Bit [4:0]
Transmission queue aging time out counter
Bit[13:5]
frame latest departure time
Bit [21:14]
TXFIFOT
Transmission FIFO Threshold in Bytes (Default =0) Only for 100M ports
Unit=8Bytes
0= Cut Through at the destination 100M port
When the value does not equal zero, it indicates the port cannot start
sending frames out, until the Tx FIFO reaches the threshold or EOF.
18.2.9 MII Serial Management Channel
These registers are part of the Management Module. They allow the upper layer services to communicate with any
one of the PHYs that are connected to the Management Module through the serial interface.
18.2.9.1 AMIIC - MII Command Register
This is a write-only register. The upper layer services write the management frame to be sent to the PHYs into this
register. The MSB (bit 31) is the first bit sent over the serial interface.
Access:
Non-Zero-Wait-State,
Direct Access,
Write only
Address:
h654
Bit [31:30]
ST
Start of frame - always = "01"
Bit [29:28]
OP
Operation code - "10" for read command and "01" for write command
Bit [27:23]
PHY_AD
5-bit PHY Address
0
qmt_cnt
31
14 13
depart_time
5 4
TxFIFO Threshold[7:0]
22 21
2 1 0
REG_AD
23 22
DATA (16-bit)
ST
OP
PHY_AD
TA
31 30 29 28 27
18 17 16 15