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參數(shù)資料
| 型號(hào)： | MDS213 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 12-Port 10/100Mbps + 1Gbps Ethernet Switch |
| 中文描述： | 12口10/100Mbps千兆以太網(wǎng)交換機(jī) |
| 文件頁(yè)數(shù)： | 43/120頁(yè) |
| 文件大?。?/td> | 1678K |
| 代理商： | MDS213 |
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MDS213
Data Sheet
43
Zarlink Semiconductor Inc.
10.1.1 Power On/Reset Configuration
On power-up, the following five Bootstrap bits, of Table 6, are used:
Table 6 - Bootstrapping Options
10.1.2 CPU Bus Clock Interface
The CPU Interface allows the CPU bus clock to operate at clock rates different from the system clock rate. The
CPU Bus Clock rate is always less than or equal to the System Clock rate.
10.1.3 Address And Data Buses
The CPU Interface provides separate, non-multiplexed address and data buses. The data bus is a synchronous,
32-bit bus that can receive 16 or 32-bit wide data. The Flash memory uses a 16-bit data bus. The data bus supports
32 bit wide data for managed and unmanaged modes. The address bus supports 10 [10:1] address bits for
managed and unmanaged modes. Each device occupies 2048 bytes of Input/Output space.
10.1.4 Bus Master
The nomenclatures "Master" and "Slave" refer to the device that possesses the CPU Interface, or Control Bus,
while the designations of "Primary" and "Secondary" refer to the device that possesses the Bus Arbiter. The primary
or secondary device is determined during Power On/Reset, bootstrap options, while the master or slave device
changes dynamically, and will be determined by the Arbiter.
In managed mode, the systems' external CPU is the permanent master device. All other devices (e.g. the MDS213)
are designated as slave devices only. In unmanaged mode, the arbiter (located within the primary device) selects
one of the devices as the Master.
Note:
In unmanaged mode, the primary device may be the Master or the Slave. The master device is the bus
master (controls the bus), while the other device is a slave device.
10.1.5 Input/Output Mapped Interface
The systems' external CPU accesses the switch devices' local memory using single-read/write or burst - read/write
I/O cycles. Burst I/O operations with auto address incrementing uses a 32-byte write data buffer and a 32-byte
cache read data buffer.
Name
Default
Functional Description
BS_BMOD
1
Bus Mode
Must be 0
BS_RW
1
Selects R/W Control polarity
0=R/W# 1=W/R#
BS_SWM
1
Switch Mode (only in Managed Mode)
0=Managed Mode 1=Unmanaged Mode
BS_PSD
1
Primary Device Enable (only in Unmanaged Mode)
0=Secondary Mode 1=Primary Mode
(The arbiter is activated in the chip with Primary Device.)
BS_RDYOP
1
Option of merger the P_RDY# and P_BRDY#
0=merged P_RDY# and P_BRDY# pin
1=Separated P_RDY# and P_BRDY# pins
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