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MDS212
Data Sheet
96
Zarlink Semiconductor Inc.
h1c0
h200
h240
h280
h2c0
ECR0_p7
ECR0_p8
ECR0_p9
ECR0_p10
ECR0_p11
Bit [0]
Bit [1]
Bit [2]
Bit [31:3]
Port is disabled when both RR & XR bits are set.
RR
XR
RE
Reserved
Reset Receiver
Reset Transmitter
RX Enable
18.2.12.2 ECR1 - MAC Port Configuration Register
Access:
Address:
Non-Zero-Wait-State,
h0x1*4
h004 ECR1_p0
h044 ECR1_p1
h084 ECR1_p2
h0c4 ECR1_p3
h104 ECR1_p4
h144 ECR1_p5
h184 ECR1_p6
h1c4 ECR1_p7
h204 ECR1_p8
h244 ECR1_p9
h284 ECR1_p10
h2c4 ECR1_p11
Direct Access,
x: port number
Write/Read
Configuration Bits
Trunking
Port Trunking ID Bits
Bit [0:2]
Bit [3]
TGID
TE
Group ID
Trunk Enable
0= Trunk disable
1= Trunk Enable
Unicast Blocking Control Bits
Bit [5:4]
Block_UC_Frame
Instructs the Rx MAC to discard incoming Unicast Frames. This
feature is used by Spanning Tree.
0X Blocking, all frames (Default state)
10 Learning but not forwarding
11 Forwarding all frames
Ingress Filter Enable
Bit [6]
IFE
Default = 0
31
3
2
1
0
RE
XR
RR
31
24
23
17
16
15
8
7
6
5
4
3
2
0
IFG
10M
IFE
BKUC
TE
TG ID