參數(shù)資料
型號(hào): MDS212CG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA456
封裝: 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456
文件頁數(shù): 67/111頁
文件大?。?/td> 1609K
代理商: MDS212CG
MDS212
Data Sheet
67
Zarlink Semiconductor Inc.
18.2.1.3 DCR1 - Signature, Revision & ID Register
Access:
Address:
Non-Zero-Wait-State,
h7C4
Direct Access,Write/Read
Bit [3:0]
Device Revision Code
Bit [6:4]
Reserved
Bit [15:8]
Signature
8-bit Device Signature
Bit [19:16] Reserved
Bit [24:20] DEV_ID
5-bit Device ID (Read/Write)
Bit [31:25] Reserved
18.2.1.4 DCR2 - Device Configuration Register
Access:
Address:
Non-Zero-Wait-State,
h7C8
Direct Access,
Write/Read
Bit [1:0] SC
System Clock Rate
Default = 00
00= 100Mhz
10=90Mhz
01 = 120Mhz
11=80Mhz
Bit [2]
IP
IRQ output polarity control Power-up default =0
0 = active low output
1 = active high output
Bit [3]
SM
System Configuration mode
0=Nonblocking (For MDS212, Always equal to 0)
1=Blocking
SRAM Memory Characteristics
Bit [4]
ML
Buffer Memory Level, which can be either 2 chips or 4 chips.
0 = 2 memory chips
Default = 0
1 = 4 memory chips
Bit [6:5] MT
Memory Chip Type
Default = 01
00 = 64K x 32-bit
01 = 128K x 32-bit
10 = 256K x 32-bit
11 = 512K x 32-bit
Bit [8:7]
Reserved
31
25
24
20
19
16
15
12 11
Signature
8
7
4
3
2
0
Dev_ID
Rev
31
27
26 25
22 21 20
19
18 17
9
8
7
6
5
4
3
2
0
1
Boot Strap
IP
MC
FE and MAC
SE Configuration
MT
ML
SM
IP
SC
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