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參數(shù)資料
| 型號： | MD80C51 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | CHMOS單片8位微控制器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 229K |
| 代理商： | MD80C51 |
AUTOMOTIVE 80C31BH/80C51BH/87C51
ABSOLUTE MAXIMUM RATINGS
*
Ambient Temperature Under Bias
b
40
§
C to
a
125
§
C
Storage Temperature àààààààààà
b
65
§
C to
a
150
§
C
Voltage on EA/V
PP
Pin to V
SS
ààààààà0V to
a
13.0V
Voltage on Any Other Pin to V
SS
àà
b
0.5V to
a
6.5V
I
OL
per I/O pin ààààààààààààààààààààààààààà15 mA
Power Dissipationàààààààààààààààààààààààààà1.5W
(Based on package heat transfer limitations, not de-
vice power consumption).
Typical Junction Temperature (T
J
) àààààààà
a
135
§
C
(Based upon ambient temperature at
a
125
§
C)
Typical Thermal Resistance Junction-to-Ambient
(
i
JA
):
PDIP àààààààààààààààààààààààààààààà75
§
C/W
PLCCàààààààààààààààààààààààààààààà46
§
C/W
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
DC CHARACTERISTICS:
(T
A
e b
40
§
C to
a
125
§
C; V
CC
e
5V
g
10% (5V
g
20% EPROM Only); V
SS
e
0V)
Symbol
Parameter
Min
Typ(1)
Max
Unit
Test
(87C51/80C51BH)
Conditions
V
IL
Input Low Voltage (Except EA)
b
0.5
0.2 V
CC
b
0.25
0.2 V
CC
b
0.45
V
CC
a
0.5
V
CC
a
0.5
0.45
(7)
V
V
IL1
Input Low Voltage to EA
0
V
V
IH
Input High Voltage (Except XTAL1, RST)
0.2V
CC
a
1.0
0.7 V
CC
a
0.1
V
V
IH1
Input High Voltage (XTAL1, RST)
V
V
OL
Output Low Voltage (Ports 1, 2, 3)
V
I
OL
e
1.6 mA
(2)
I
OL
e
3.2 mA
(2)
I
OH
e b
60
m
A
I
OH
e b
10
m
A
I
OH
e b
800
m
A
I
OH
e b
80
m
A
(3)
V
IN
e
0.45 V
V
OL1
Output Low Voltage (Port 0, ALE, PSEN)
0.45
(7)
V
V
OH
Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)
2.4
V
0.9 V
CC
V
V
OH1
Output High Voltage (Port 0 in
External Bus Mode)
2.4
V
0.9 V
CC
V
I
IL
Logical 0 Input Current (Ports 1, 2, 3)
b
75
m
A
I
TL
Logical 1-to-0 transition current
(Ports 1, 2, 3)
b
750
m
A
(4)
I
LI
Input Leakage Current (Port 0)
g
10
m
A
V
IN
e
V
IL
or V
IH
I
CC
Power Supply Current:
Active Mode
@
12 MHz
(5)
Idle Mode
@
12 MHz
(5)
Power Down Mode
11.5
1.3
3
25/20
6/5
100/75
mA
mA
m
A
(6)
V
CC
e
2.2V to 5.5V
RRST
Internal Reset Pulldown Resistor
50
300
K
X
CIO
Pin Capacitance
10
pF
NOTES:
1. ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
s of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-0 transitions during bus operations. In the worst cases (capacitive loading
l
100pF), the noise pulse on the ALE pin may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
3. Capacitive loading on Ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9 V
CC
specification when the address bits are stabilizing.
8
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