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11028E–ATARM–22-Apr-13

The bits are shifted out on the MISO line and sampled on the MOSI line.

(For more information on BITS field, see also, the (Note:) below the register table; Section 29.8.9

When all the bits are processed, the received data is transferred in the Receive Data Register

and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new

data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data

is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit.

When a transfer starts, the data shifted out is the data present in the Shift Register. If no data

has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred.

If no data has been received since the last reset, all bits are transmitted low, as the Shift Regis-

ter resets at 0.

When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the

TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls

and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in

SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent

updates of critical variables with single transfers.

Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no

character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last

load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received

character is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the

Figure 29-13 shows a block diagram of the SPI when operating in Slave Mode.

Figure 29-13. Slave Mode Functional Bloc Diagram

Shift Register

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