參數(shù)資料
型號: MCZ33884EG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Switch Monitor Interface
中文描述: 開關(guān)顯示器接口
文件頁數(shù): 7/21頁
文件大?。?/td> 251K
代理商: MCZ33884EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33884
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V
V
DD
5.25 V, 9.0 V
V
PWR
16 V, -40
°
C
T
C
105
°
C, unless otherwise
noted. Typical values, where applicable, reflect the approximate parameter mean with V
PWR
= 13 V, T
A
= 25
°
C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT TIMING
Pulse Wetting Current Duration
t
PULSE
3.0
34
43
ms
Interrupt Delay Time
t
INT(DELAY)
2.5
13
ms
SCLK Frequency vs. SO Load Capacitance
200 pF
160 pF
120 pF
f
SCLK
3.2
3.5
4.0
MHz
DIGITAL INTERFACE TIMING
Input Logic Voltage Thresholds
(13)
V
IN(LOGIC)
0.2 x V
DD
0.7 x V
DD
V
SO High State Output Voltage (I
OH
= 1 mA)
V
OH(SO)
3.5
V
SO Low State Output Voltage (I
OL
= 1 mA)
V
OL(SO)
0.4
V
SO Tri-State Leakage Current (CS = 0.7 V
DD
, V
SO
= 0 to V
DD
)
I
T(SO)
-40
40
μA
SI Pull Down Current (SI = VDD)
I
SI
5.0
35
μA
SCLK Input Current (0 V = VDD)
I
SCLK
-10
10
μA
CS Pull-Up Current (CS = 0 V)
I
CS
-25
-5.0
μA
RST Pull Down Current (RST = 0 V)
I
RST
5.0
35
μA
INT Low State Output Voltage (I
OL
= 0.5 mA)
Input Capacitance on SCLK, SI, Tri-State, SO, CS
(13)
V
OL(INT)
0.4
V
C
IN
20
pF
Falling Edge of CS to Rising Edge of SCLK
(13)
(Required set-up time)
t
LEAD
100
140
ns
Falling Edge of SCLK to Rising Edge of CS (Required set-up time)
t
LAG
50
ns
SI to Rising Edge of SCLK (Required set-up time)
t
SU2
25
45
ns
Rising Edge of SCLK to SI (Required hold time)
t
H2
25
45
ns
SO to Rising Edge of SCLK
t
SU1
90
125
ns
Rising Edge of SCLK to Falling Edge of SO (Hold time)
t
H1
90
125
ns
SO Rise Time, SO Fall Time (C
L
= 200 pF)
t
R(SO)
t
F(SO)
30
50
ns
SI, CS, SCLK Incoming Signal Rise Time
(13)
t
R(SI)
50
ns
SI, CS, SCLK Incoming Signal Fall Time
(13)
t
F(SI)
50
ns
Time from Falling Edge of CS to SO Low Impedance
(13)
t
SO(EN)
80
110
ns
Notes
9
10
11
12
Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, SYNC, MASL. See page five.
This parameter is guaranteed by design, however, it has not been production tested.
Rise and fall time for incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output states data to be available at SO pin.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MCZ33887EKR2DH 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:5.0 A H-Bridge with Load Current Feedback