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參數(shù)資料
| 型號(hào)： | MCZ33742SEGR2 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁(yè)數(shù)： | 32/65頁(yè) |
| 文件大?。?/td> | 1158K |
| 代理商： | MCZ33742SEGR2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
32
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
MCU FLASH PROGRAMMING CONFIGURATION
To allow for new software to be loaded into a SBC’s MCU
NVM or to standalone EEPROM or Flash, the 33742 is
capable of having (1) VSUP applied to it to from an external
power 5.0 V supply and (2) having the RST and the WDOG
outputs pins eternally forced to 0.0 V or 5.0 V without
damaging the device.
This allows the SBC to be externally powered and off-
board signals to be applied to the reset pins. No functions of
the 33742 are operating.
Figure 18
illustrates a typical
configuration for the connection of programming and
debugging tools.
The VSUP should be left open or forced to a value equal
to or above V.
The VDD regulator uses an internal pass transistor
between VSUP and the VDD output pin. Biasing the VDD
output pin with a voltage greater than VDD
potential will force
current through the body diode of the internal pass transistor
to the VSUP pin.
The RST pin is periodically pulled LOW for the t
RSTDUR
time (device in Reset mode), before being pulled to VDD for
350 ms typical (device in Normal Request mode). During the
time reset is LOW, the RST pin sinks 5.0 mA maximum
(I
PDW
).
Figure 18. Simplified Schematic for Microcontroller Flash Programming
33742
MCU with
Flash Memory
VDD
RST
WDOG
VSUP (Open or > 5.0 V
Programming Bus
Note
External supply and sources applied to VDD,
RST
, and
WDOG
test points on application circuit board.
5.0 V
Programming Tool
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