參數(shù)資料
型號: MCZ33291EG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Eight-Output Switch with Serial Peripheral Interface I/O
中文描述: 8輸出開關串行外設接口的I / O
文件頁數(shù): 21/26頁
文件大?。?/td> 379K
代理商: MCZ33291EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
33291
FUNCTIONAL DESCRIPTION
sometimes be determined over hard short faults and
overtemperature faults by observing the time required for the
device to recover. However, in general overcurrent and
overtemperature faults cannot be differentiated in normal
application usage.
An advantage of the synchronous serial output is multiple
faults can be detected with only one (SO) pin being used for
fault status reporting.
If V
PWR
experiences an overvoltage condition, all outputs
will immediately be turned OFF and remain latched OFF. A
new command word is required to turn the outputs back ON
following an overvoltage condition.
Output Voltage Clamping
Each output of the 33291 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of the
output. Each clamp independently limits the drain-to-source
voltage to 53 V at drain currents of 0.5 A and keeps the
output transistors from avalanching by causing the transient
energy to be dissipated in the linear mode (see
Figure 21
).
The total energy clamped (E
J
) can be calculated by
multiplying the current area under the current curve (I
A
) times
the clamp voltage (V
CL
) times the duration the clamp is active
(t).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.5 A, indicates the maximum
energy to be 50 mJ at 150
°
C junction temperature per output.
Figure 21. Output Voltage Clamping
THERMAL CHARACTERIZATION
THERMAL MODEL
Logic functions take up a very small area of the die and
generate negligible power. In contrast, the output transistors
take up most of the die area and are the primary contributors
of power generation. The thermal model illustrated in
Figure 22
, page
22
, was developed for the 33291 mounted
on a typical PC board. The model is accurate for both steady
state and transient thermal conditions. The components R
d0
through R
d7
represent the steady state thermal resistance of
the silicon die for transistor outputs 0 through 7, while C
d0
through C
d7
represent the corresponding thermal
capacitance of the silicone die translator outputs and plastic.
The device area and die thickness determine the values of
these specific components.
The thermal impedance of the package from the internal
mounting flag to the outside environment is represented by
the terms R
PKG
and C
PKG
. The steady state thermal
resistance of leads and the PC board make up the steady
state package thermal resistance, R
pkg
. The thermal
capacitance of the package is made up of the combined
capacitance of the flag and the PC board. The mode
compound was not modeled as a specific component but it is
factored into the other overall component values.
The battery voltage in the thermal model represents the
ambient temperature the device and PC board are subjected
to. The I
PWR
current source represents the total power
dissipation and is calculated by totalling the power dissipation
of each individual output transistor. This is easily
accomplished by knowing R
DS(ON)
and load current of the
individual outputs.
Very satisfactory steady state and transient results are
experienced with this thermal model. Tests indicate the
model accuracy to have less than 10 percent error. Output
interaction with an adjacent output is believed to be the main
contributor to the thermal inaccuracy. Tests indicate little or
no detectable thermal effects caused by distant output
transistors isolated by one or more other outputs. Tests were
conducted with the device mounted on a typical PC board
placed horizontally in a 33 cubic inch still air enclosure. The
PC board was made of FR4 material measuring 2.5 by
2.5 inches, having double-sided circuit traces of 1.0 ounce
copper soldered to each device pin. The board temperature
was measured with thermal couple soldered to the board
surface one inch away from the center of the device. The
ambient temperature of the enclosure was measured with a
second thermal couple located over the center of one inch
distance from device.
THERMAL PERFORMANCE
Figure 22
illustrates the worst case thermal component
parameters values for the 33291 in the 24-lead SOIC wide
body surface mount package. Pins 5, 6, 7, 8, 17, 18, 19, and
20 of the package were connected directly to the lead frame
flag. The parameter values indicated take into account
adjacent output combinations. The characterization was
conducted over power dissipation levels of 0.7 W to 17 W.
The junction-to-ambient temperature resistance was found to
be 40°C/W with a single output active (34°C/W with all
outputs dissipating equal power 0 and the thermal resistance
from junction-to-PC board (R
JUNCTION-BOARD
) to be 30°C/W
(board temperature, measure one inch from device center).
The junction-to-heatsink lead resistance was found again to
approximate 10°C/W. Devoting additional PC board metal
around the heatsinking pins for this package improved the
R
PKG
from 33° to 31°C/W.
Current
Area (I
A
)
VPWR
Time
GND
Drain-to-Source ON
Voltage (V
DS(ON)
)
Drain Current
(ID = 0.5 A)
Drain-to-Source Clamp
Voltage (VCL = 65 V)
Drain Voltage
Clamp Energy
(E
J
= I
A
x V
CL
x t)
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