參數(shù)資料
型號: MCZ33291EG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Eight-Output Switch with Serial Peripheral Interface I/O
中文描述: 8輸出開關串行外設接口的I / O
文件頁數(shù): 10/26頁
文件大?。?/td> 379K
代理商: MCZ33291EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
33291
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Figure 7. Valid Data Delay Time and
Valid Time Waveforms
Figure 8. Enable and Disable Time Waveforms
Figure 9. Switching Time Test Circuit
Figure 10. Output Fault Unlatch Disable
Delay Test Circuit
SCLK
SO
(Low-to-High)
SO
(High-to-Low)
t
VALID
t
DLY(LH)
t
DLY(HL)
0.2 V
DD
0.7 V
DD
t
R (SO)
t
F (SO)
0.7 V
DD
0.2 V
DD
0.7 V
DD
50%
0.2 V
DD
0
t
R (SI)
< 50 ns
< 50 ns
t
F (SI)
5.0 V
V
OH
V
OL
V
OH
V
OL
SO (Low-to-High) is for an output with internal conditions such that
the low-to-high transition of
CS
causes the SO output to switch from
high to low.
90%
10%
10%
10%
90%
90%
CS
SO
(High-to-Low)
SO
(Low-to-High)
0.2 V
DD
0.7
V
DD
< 50 ns
< 50 ns
t
R(SI)
t
F(SI)
t
SO(EN)
t
SO(DIS)
t
SO(EN)
t
SO(DIS)
VTri-State
5.0 V
0
t
SO(DIS)
VTri-State
VOH
1. SO (high-to-low) waveform is for SO output with internal conditions such
that SO output is low except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state; e.g., open load.
2. SO (low-to-high) waveform is for SO output with internal conditions such
that SO output is high except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state; e.g., shortened load.
C
L
represents the total capacitance of the test fixture and probe.
CS
Output
C
L
33291
Under
Test
V
DD
= 5.0 V
V
PWR
= 14 V
R
L
= 26
CS
Output
C
L
= 20 pF
33291
Under
Test
V
DD
= 5.0 V
V
PWR
= 11 V
C
L
represents the total capacitance of the test fixture and probe.
Ι
L
= 2.0 Α
(Ουτπυτ ΟΝ)
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