參數(shù)資料
型號(hào): MCVVQ111AFB
廠商: MOTOROLA INC
元件分類(lèi): 顯示驅(qū)動(dòng)器
英文描述: VirtuoVue Monochrome Video Display Driver
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PQFP48
封裝: PLASTIC, LQFP-48
文件頁(yè)數(shù): 6/18頁(yè)
文件大?。?/td> 175K
代理商: MCVVQ111AFB
MOTOROLA
REV 0 Page 6
Jan. 2002
MCVVQ111AFB
PDR falling edge after SLEEP falling edge
-
10
-
nS
PIN DESCRIPTION
Pin No
Pin Name
Description
1
SLEEP
Logic level input. A logic low sets the IC into the sleep mode. Internal 500K pull-
down provided.
2
HODL Select
Used for HODL selection.
Logic 1: column inversion output on HODL for ABNORMAL video
(such as cue/review/pause mode)
Logic 0: pixel inversion output on HODL for NORMAL video
Also refer the description of pin 37
3
OSD In
Input for the OSD signals. See text for required signal levels.
4,12
AGND
Ground for the PLL section.
5
Video Input
Input for standard level monochrome video,525 or 625 lines. Source impedance must
be less than 500.
6
Clamp
Clamp capacitor, to ground, for the video black level clamp.
7
PLL Filter
Filter pin for the internal horizontal PLL.
8
Gain
DC control for the gain of the video signal path. Adjustment range is +/- 3.5dB.
9
SYFltr
Filter pin for the sync separator. Capacitor to ground is required.
10
525/625
Set low if the input video is a 525 line system (NTSC). Set high for 625 line systems.
Internal 500K pull-down provided.
11
DGND
Ground for the digital sections and signals.
13
PDR
Power Down reset output to the LCD panel. Active low.
14
VIDH
Upper video drive signal to the LCD panel.
15
VCK
Vck control signal to the LCD panel.
16
VPL
Vertical start pulse output to the LCD panel.
17
HODL
Inversion control output to the LCD panel.
18
VCOM
Internally generated supply for the LCD panel. Nominally +5.8 volts.
19
VEE
Internally generated supply for the LCD panel. Nominally +2.0 volts.
20
VDD
Internally generated supply for the LCD panel. Nominally +9.0 volts.
21
VSS
Reference ground for the LCD panel.
22
VREF
Internally generated supply for the LCD panel. Nominally VBat/2.
23
HPL
Horizontal start pulse output to the LCD panel.
24
HCK
Horizontal clock output to the LCD panel.
25
RENE
Even Row Enable output to the LCD panel.
26
RENO
Odd Row Enable output to the LCD panel.
27
VIDL
Lower video drive signal to the LCD panel.
28
VIDLC
Connect to VIDHC through a compensation capacitor.
29
VIDHC
Connect to VIDLC through a compensation capacitor,
30
Black Level
DC Control to adjust the video output black level for normal video and OSD signals.
31
N/C
Not connected
SYSTEM TIMING
Parameter
Min
Typ
Max
Unit
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