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參數(shù)資料
| 型號(hào)： | MCVVQ111AFB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | VirtuoVue Monochrome Video Display Driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 14/18頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | MCVVQ111AFB |
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MOTOROLA
REV 0 Page 14
Jan. 2002
MCVVQ111AFB
HCK (pin 24) - Horizontal Clock. This square wave output has a frequency of 384x the video horizontal frequency. This
output is present continuously in both fields.
RENE (pin 25) - Row Enable (Even) - This active low output occurs during the active video time of each even numbered
line. It is present for video lines 22 through 260.
RENO (pin 26) - Row Enable (Odd) - This active low output occurs during the active video time of each odd numbered line.
It is present for video lines 23 through 261.
HODL Selection
- During cue/review/pause mode of the camcorder operation or under noisy environment, which defined
as Abnormal Video Mode, the HODL should be under Column Inversion Output. HODL Selection(pin 2) is set to HIGH (Column
Inversion) for abnormal video mode and LOW (Pixel Inversion) for normal mode. The switching frequency of HODL polarity can
be either VF/2 Hz or VF/4 Hz depending on the setting of the HODL_INV_FREQ(pin 37). VF is defined as vertical frequency.
The minimum voltage level for logic HIGH of HODL SEL is 0.66xVBAT volts and the maximum voltage level for logic
LOW is 0.33xVBAT volts.
Switching frequency of HODL polarity
:
OSD Input
- If the OSD display information is not contained in the composite video signal, then OSD information can be
applied to pin 3. The signal levels at this pin must conform to that shown in Figure 11, and must be externally generated and
synchronized with the video. The sync outputs at pins 45 and 46 can be used for synchronization.
Normally, pin 3 is to be at ground to display the video applied at pin 5. When the OSD input signal at pin 3 exceeds the
OSD threshold (0.75 volt), the internal switch transfers the video amplifiers’ outputs to the black level, causing a black display at
the LCD panel. This black time can be, e.g., a border. The OSD Black level is the same as that set for the normal video black level,
and is set by the voltage at pin 30 (see Figure 2).
When the OSD input signal is increased past the White threshold (2.25 volts), the video amplifiers’ outputs go to the White
Level.
Formation of the on-screen characters is accomplished by appropriate timing of the signal at pin 3, as shown in the example
in Figure 12. The OSD input signal must be returned to ground to resume displaying the video signal at pin 5. If the OSD input pin
is not used, it must be connected to ground.
The default OSD contrast is 92.5%(1.475V).
Sleep Mode
- The Sleep mode, activated by setting SLEEP pin low, will shut off the entire IC by removing all power
supply voltages and the driving signals from the LCD display panel. This mode results in power consumption by the IC of less
than 1 mW.
PDR
- The PDR section prevents invalid video display during the power up or when VDDH drops below 10 volts.
The PDR will be released if following two conditions are met:
. 333 - 400 ms elapses after power up
. VDDH is no less than 10 volts.
Only if both of the above conditions meet, the display panel will be enabled.
The PDR scheme can be either scheme 1 or scheme 2 depending on the setting of SEL_PDR(pin 42). The difference between
these two schemes is: When PDR is asserted during VBlanking, 3 RENE/RENO pulses will be generated under scheme 2 but no
RENE/RENO pulse will be generated under scheme 1.
HODL_INV_FREQ
PAL
NTSC
0
25 Hz
30 Hz
1
12.5 Hz
15 Hz
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