
MCP6546/7/8/9
DS21714C-page 12
2003 Microchip Technology Inc.
3.0
APPLICATIONS INFORMATION
The MCP6546/7/8/9 family of push-pull output
comparators are fabricated on Microchip’s state-of-the-
art CMOS process. They are suitable for a wide range
of applications requiring very low power consumption.
3.1
Comparator Inputs
The MCP6546/7/8/9 comparator family uses CMOS
transistors at the input. They are designed to prevent
phase inversion when the input pins exceed the supply
voltages. Figure 2-37 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages.
With this topology, the input voltage is 0.3V above V
DD
and 0.3V below V
SS
. Therefore, the input offset
voltage is measured at both V
SS
- 0.3V and V
DD
+ 0.3V
to ensure proper operation.
The maximum operating input voltages that can be
applied are V
SS
- 0.3V and V
DD
+ 0.3V. Voltages on the
inputs that exceed this absolute maximum rating can
cause excessive current to flow and permanently
damage the device. In applications where the input pin
exceeds the specified range, external resistors can be
used to limit the current below ±2 mA, as shown in
Figure 3-1.
FIGURE 3-1:
should be used to limit excessive input current if
either of the inputs exceeds the absolute
maximum specification.
An input resistor (R
IN
)
3.2
Open-Drain Output
The open-drain output is designed to make level-
shifting and wired-OR logic easy to implement. The
output can go as high as 10V for 9V battery-powered
applications. The output stage minimizes switching
current (shoot-through current from supply-to-supply)
when the output changes state. See Figures 2-15, 2-17
and 2-32 through 2-36, for more information.
3.3
MCP6548 Chip Select (CS)
The MCP6548 is a single comparator with a chip select
(CS) option. When CS is pulled high, the total current
consumption drops to 20 pA (typ). 1 pA (typ) flows
through the CS pin, 1 pA (typ) flows through the output
pin and 18 pA (typ) flows through the V
DD
pin, as
shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS low, the comparator is enabled. If the CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
3.4
Externally Set Hysteresis
Greater flexibility in selecting hysteresis, or input trip
points, is achieved by using external resistors.
Input offset voltage (V
OS
) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (V
HYST
) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other, thus reducing dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control). The MCP6546/7/8/9 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV), and large enough to eliminate
output chattering caused by the comparator’s own
input noise voltage (200 μVp-p).
FIGURE 3-2:
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
The MCP6546/7/8/9
RIN
VSS
Minimum expected VIN
2 mA
(
)
–
≥
RIN
-Maximum expected VIN
(
)
VDD
–
2 mA
≥
V
IN
R
IN
V
OUT
MCP654X
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
0
100
200
300
400
500
600
700
800
900
1000
Time (100 ms/div)
O
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
I
V
OUT
V
IN
–
Hysteresis
V
DD
= 5.0V
V
IN
+ = 2.75V