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參數(shù)資料
型號： MCP4725EV
廠商： Microchip Technology
文件頁數(shù)： 25/50頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR MCP4725
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 100k ~ 3.4M
數(shù)據(jù)接口： I²C
設(shè)置時間： 6µs
DAC 型： 電壓
工作溫度： -40°C ~ 125°C
已供物品： 2 板，CD
已用 IC / 零件： MCP4725
產(chǎn)品目錄頁面： 673 (CN2011-ZH PDF)
2009 Microchip Technology Inc.
DS22039D-page 31
MCP4725
High Speed Mode (Note 5)
Clock frequency
fSCL
0—
3.4
MHz
Cb = 100 pF
0—
1.7
MHz
Cb = 400 pF
Clock high time
THIGH
60
—
ns
Cb = 100 pF, fSCL = 3.4 MHz
120
—
ns
Cb = 400 pF, fSCL = 1.7 MHz
Clock low time
TLOW
160
—
ns
Cb = 100 pF, fSCL = 3.4 MHz
320
—
ns
Cb = 400 pF, fSCL = 1.7 MHz
SCL rise time
TR:SCL
—
40
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
—
80
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
SCL fall time
TF:SCL
—
40
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
—
80
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
SDA rise time
TR: DAT
—
80
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
—
160
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
SDA fall time
TF: DAT
—
80
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
—
160
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
Data hold time
THD:DAT
0
—
70
ns
Cb = 100 pF, fSCL = 3.4 MHz
0
—
150
ns
Cb = 400 pF, fSCL = 1.7 MHz
Output valid from clock
(Notes 2 and 3)
TAA
—
150
ns
Cb = 100 pF, fSCL = 3.4 MHz
—
310
ns
Cb = 400 pF, fSCL = 1.7 MHz
START condition hold time
THD:STA
160
—
ns
After this period, the first clock
pulse is generated
START (Repeated) condition
setup time
TSU:STA
160
—
ns
Data input setup time
TSU:DAT
10
—
ns
STOP condition setup time
TSU:STO
160
—
ns
TABLE 7-1:
I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V, VSS = 0V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is ensured by characterization and not 100% tested.
2:
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3:
If this parameter is too short, it can create an unintended START or STOP condition to other devices on the same bus
line. If this parameter is too long, Clock Low time (TLOW) can be affected.
4:
For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5:
All timing parameters in high-speed modes are tested at VDD = 5V.
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