FIGURE 1-2: SPI Timing Waveform (Mode = 11). TABLE 1-2: SP" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCP4331T-104E/ML
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 5/35闋�
鏂囦欢澶�?銆�?/td> 0K
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妯欐簴鍖呰锛� 3,300
鎺ョ墖锛� 129
闆婚樆锛堟瓙濮嗭級锛� 100k
闆昏矾鏁�(sh霉)锛� 4
婧害绯绘暩(sh霉)锛� 妯欐簴鍊� 150 ppm/°C
瀛樺劜鍣ㄩ鍨嬶細 鏄撳け
鎺ュ彛锛� 4 绶� SPI锛堣姱鐗囬伕鎿囷級
闆绘簮闆诲锛� 1.8 V ~ 5.5 V
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-VFQFN 瑁搁湶鐒婄洡
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-QFN 瑁搁湶鐒婄洡锛�4x4锛�
鍖呰锛� 甯跺嵎 (TR)
2010 Microchip Technology Inc.
DS22242A-page 13
MCP433X/435X
FIGURE 1-2:
SPI Timing Waveform (Mode = 11).
TABLE 1-2:
SPI REQUIREMENTS (MODE = 11)
#
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
鈥�10
MHz VDD = 2.7V to 5.5V
鈥�1
MHz VDD = 1.8V to 2.7V
70
CS Active (VIL or VIHH) to SCK input
TcsA2scH
60
鈥�
ns
71
SCK input high time
TscH
45
鈥�
ns
VDD = 2.7V to 5.5V
500
鈥�
ns
VDD = 1.8V to 2.7V
72
SCK input low time
TscL
45
鈥�
ns
VDD = 2.7V to 5.5V
500
鈥�
ns
VDD = 1.8V to 2.7V
73
Setup time of SDI input to SCK
edge
TDIV2scH
10
鈥�
ns
VDD = 2.7V to 5.5V
20
鈥�
ns
VDD = 1.8V to 2.7V
74
Hold time of SDI input from SCK
edge
TscH2DIL20
鈥�
ns
77
CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ
鈥�
50
ns
80
SDO data output valid after SCK
edge
TscL2DOV
鈥�
70
ns
VDD = 2.7V to 5.5V
170
ns
VDD = 1.8V to 2.7V
83
CS Inactive (VIH) after SCK edge
TscH2csI
100
鈥�
ns
VDD = 2.7V to 5.5V
1ms
VDD = 1.8V to 2.7V
84
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
TcsA2csI
50
鈥�
ns
Note 1:
This specification by design.
CS
SCK
SDO
SDI
70
71
72
73
74
75, 76
77
78
79
80
SDI
MSb
LSb
BIT6 - - - - - -1
MSb IN
BIT6 - - - -1
LSb IN
83
84
VIH
VIL
VIHH
VIH
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