參數(shù)資料
型號(hào)： MCP3903T-E/SS
廠商： Microchip Technology
文件頁數(shù)： 10/15頁
文件大小： 0K
描述： IC AFE 24BIT 64KSPS 6CH 28SSOP
產(chǎn)品培訓(xùn)模塊： MCP3903 6-Channel Energy Measurement Analog Front End
標(biāo)準(zhǔn)包裝： 2,100
位數(shù)： 24
通道數(shù)： 6
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
MCP3903
DS25048B-page 4
2011 Microchip Technology Inc.
A011
CHn+-
Analog Input Absolute
Voltage
-1
+1
V
All analog input channels,
measured to AGND
A012
AIN
Analog Input Leakage
Current
1nA
A013
(CHn+-
CHn-)
Differential Input Voltage
Range
500 /
GAIN
mVP
A014
VOS
Offset Error
-3
3
mV
A015
Offset Error Drift
1
μV/C
From -40°C to 125°C
A016
GE
Gain Error
-3
3
%
All Gains
A017
Gain Error Drift
—
2
—
ppm/°C From -40°C to 125°C
A018
INL
Integral Non-Linearity
15
ppm
GAIN = 1, DITHER = ON
A019
ZIN
Input Impedance
350
—
k
Ω
Proportional to 1/AMCLK
A020
SINAD
Signal-to-Noise and
Distortion Ratio
89
91
—
dB
T = 25°C
80
81.5
dB
A021
THD
Total Harmonic Distortion
-100
-97
dB
OSR = 256, DITHER = ON;
-90
-87
dB
A022
SNR
Signal To Noise Ratio
90
91.5
dB
T = 25°C
80
81.5
dB
A023
SFDR
Spurious Free Dynamic
Range
102
dB
OSR = 256, DITHER = ON;
91
dB
A024
CTALK
Crosstalk (50 / 60 Hz)
—
-115
—
dB
OSR = 256, DITHER = ON;
A025
AC PSRR AC Power Supply Rejection
—
-68
—
dB
AVDD = 5V + 1Vpp @ 50 Hz
A026
DC PSRR DC Power Supply Rejection
—
-68
—
dB
AVDD = 4.5 to 5.5V, DVDD =
3.3V
A027
CMRR
DC Common Mode Rejection
Ratio
—-75
—
dB
VCM varies from -1V to +1V;
Oscillator Input
TABLE 1-1:
ANALOG SPECIFICATIONS TARGET TABLE
(CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to
3.6V, Internal VREF, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,
GAIN = 1, VIN = 1VPP = 353mVRMS @ 50/60 Hz.
Param.
Num.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Test Conditions
Note 1:
This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or
instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range,
VIN = -0.5 dBFS @ 50/60 Hz = 333 mVRMS, VREF = 2.4V.
2:
See terminology section for definition.
3:
This parameter is established by characterization and not 100% tested.
4:
For these operating currents, the following configuration bit settings apply: Config Register Settings:
SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.
5:
For these operating currents, the following configuration bit settings apply: Config Register Settings:
SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.
6:
Applies to all gains. Offset error is dependant on PGA gain setting.
7:
Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to
the part with no risk for damage.
8:
For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits
off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a
crystal, CLKEXT bit should be equal to ‘0’.
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